公开(公告)号：US20200075492A1

公开(公告)日：2020-03-05

申请号：US16216946

申请日：2018-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joo Young CHOI ,  Doo Hwan LEE ,  Da Hee KIM ,  Jae Hoon CHOI ,  Byung Ho KIM

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes a connection member having a first surface and a second surface opposing each other and including a first redistribution layer on the second surface and at least one second redistribution layer on a level different from a level of the first redistribution layer; a semiconductor chip on the first surface of the connection member; a passivation layer on the second surface of the connection member, and including openings; UBM layers connected to the first redistribution layer through the openings; and electrical connection structures on UBM layers. An interface between the passivation layer and the UBM layers has a first unevenness surface, an interface between the passivation layer and the first redistribution layer has a second unevenness surface, connected to the first unevenness surface, and the second unevenness surface has a surface roughness greater than a surface roughness of the second redistribution layer.

公开(公告)号：US20200075517A1

公开(公告)日：2020-03-05

申请号：US16282980

申请日：2019-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung Ho KIM ,  Jae Hoon CHOI ,  Joo Young CHOI

IPC: H01L23/00

Abstract: A semiconductor package includes a connection member having first and second surfaces opposing each other and including at least one insulating layer and redistribution layer, the redistribution layer including a via penetrating through the insulating layer and a RDL pattern connected to the via while being located on an upper surface of the insulating layer; a semiconductor chip disposed on the first surface and including a connection pad connected to the redistribution layer; and an encapsulant disposed on the first surface and encapsulating the semiconductor chip. The redistribution layer includes a seed layer disposed on a surface of the insulating layer and a plating layer disposed on the seed layer. An interface between the insulating layer and a portion of the seed layer constituting the via includes a first uneven surface with a surface roughness of 30 nm or more.