公开(公告)号：US20170222630A1

公开(公告)日：2017-08-03

申请号：US15417339

申请日：2017-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Woo KIM ,  Ju Hyun KANG ,  Min Su KIM ,  Ka Ram LEE

IPC: H03K3/012 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/35625

Abstract: A semiconductor device may include a master latch that stores an input data signal, using a local power supply voltage and a clock signal, and outputs the input data signal to a first output signal; a slave latch that stores the first output signal, using a global power supply voltage, the clock signal and a retention signal, and outputs a second output signal; a first logic gate that receives input of one signal and another signal of the retention signal, the clock signal and the reset signal, and outputs a first control signal generated by performing a first logical operation; and a second logic gate that receives input of the rest of the retention signal, the clock signal and the reset signal, and the first control signal, and performs a second logical operation to at least one of the master latch and the slave latch.