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    SEMICONDUCTOR DEVICE INCLUDING RETENTION RESET FLIP-FLOP
    4.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING RETENTION RESET FLIP-FLOP 审中-公开

    公开(公告)号：US20170222630A1

    公开(公告)日：2017-08-03

    申请号：US15417339

    申请日：2017-01-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong Woo KIM ,  Ju Hyun KANG ,  Min Su KIM ,  Ka Ram LEE

    IPC: H03K3/012 ,  H03K3/3562

    CPC classification number: H03K3/012 ,  H03K3/35625

    Abstract: A semiconductor device may include a master latch that stores an input data signal, using a local power supply voltage and a clock signal, and outputs the input data signal to a first output signal; a slave latch that stores the first output signal, using a global power supply voltage, the clock signal and a retention signal, and outputs a second output signal; a first logic gate that receives input of one signal and another signal of the retention signal, the clock signal and the reset signal, and outputs a first control signal generated by performing a first logical operation; and a second logic gate that receives input of the rest of the retention signal, the clock signal and the reset signal, and the first control signal, and performs a second logical operation to at least one of the master latch and the slave latch.

    SEMICONDUCTOR CIRCUIT
    5.
    发明申请
    SEMICONDUCTOR CIRCUIT 有权

    公开(公告)号：US20220149821A1

    公开(公告)日：2022-05-12

    申请号：US17385182

    申请日：2021-07-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun Chul HWANG ,  Min Su KIM

    IPC: H03K3/037

    Abstract: A semiconductor circuit may include a first flip-flop configured to output a first input data as a first output signal in response to an inverted input clock signal, a second flip-flop configured to output a second input data as a second output signal in response to an input clock signal, a glitch-free circuit configured to receive the inverted input clock signal, the input clock signal, the first output signal, and the second output signal, and to determine a voltage level of a node on the basis of the inverted input clock signal, the input clock signal, the first output signal, and the second output signal, and an inverter configured to output an output clock signal obtained by inverting the voltage level of the node determined by the glitch-free circuit. The glitch-free circuit does not include a transistor having a gate connected to the node.

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210119617A1

    公开(公告)日：2021-04-22

    申请号：US16866941

    申请日：2020-05-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun LEE ,  Min Su KIM ,  Ah Reum KIM

    IPC: H03K3/3562 ,  H01L23/528 ,  H01L27/02

    Abstract: A semiconductor device is provided. The semiconductor device includes a clock gate line supplying a clock signal, an inverted clock gate line disposed in parallel to the clock gate line and supplying an inverted clock signal, a first latch circuit performing a first latch operation based on the clock signal and the inverted clock signal and a second latch circuit disposed on a side of the first latch circuit in a first direction, receiving an output of the first latch circuit, and operating based on the clock signal and the inverted clock, wherein the clock gate line and the inverted clock gate line extend in the first direction and are shared by the first and second latch circuits.

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20170244394A1

    公开(公告)日：2017-08-24

    申请号：US15427444

    申请日：2017-02-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji Kyum KIM ,  Dae Seong LEE ,  Min Su KIM

    IPC: H03K3/356 ,  H01L27/105 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092

    CPC classification number: H03K3/356156 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1052

    Abstract: A semiconductor device includes: first through fourth active regions spaced apart from one another; a first gate line disposed to overlap with the first and second active regions, but not with the third and fourth active regions, and to extend in a first direction; a second gate line disposed to overlap with the third and fourth active regions, but not with the first and second active regions, and to extend in the first direction while being spaced apart from the first gate line; and a dummy gate line disposed to overlap with the first through fourth active regions and a field region, to be spaced apart from the first and second gate lines in a second direction, and to extend in the first direction, wherein a signal input to the first or second active region is transmitted to the third or fourth active region.

    SEMICONDUCTOR DEVICE COMPRISING LOW POWER RETENTION FLIP-FLOP
    10.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING LOW POWER RETENTION FLIP-FLOP 审中-公开

    公开(公告)号：US20170222633A1

    公开(公告)日：2017-08-03

    申请号：US15399146

    申请日：2017-01-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong Woo KIM ,  Min Su KIM ,  Ah Reum KIM ,  Chung Hee KIM

    IPC: H03K3/3562 ,  H03K3/037

    Abstract: Provided is a semiconductor device including low power retention flip-flop. The semiconductor device includes a first line to which a global power supply voltage is applied, a second line to which a local power supply voltage is applied, the second line being separated from the first line, a first operating circuit connected to the second line to use the local power supply voltage, a first power gating circuit determining whether the local power supply voltage is applied to the first operating circuit and a first retention flip-flop connected to the first line and the second line, wherein the first retention flip-flop comprises a first circuit including a master latch, a second circuit including a slave latch, and a first tri-state inverter connected between the master latch and the slave latch.

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