公开(公告)号：US11210232B2

公开(公告)日：2021-12-28

申请号：US16562011

申请日：2019-09-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Boem Park ,  Moinul Syed ,  Ju-Hee Choi

IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/0873 ,  G06F12/1027

Abstract: A processor includes a page table walk cache that stores address translation information, and a page table walker. The page table walker fetches first output addresses indicated by first indexes of a first input address by looking up the address translation information and at least a part of page tables, and compares a matching level between second indexes of a second input address and the first indexes of the first input address with a walk cache hit level obtained by looking up the page table walk cache using the second indexes.

公开(公告)号：US11216385B2

公开(公告)日：2022-01-04

申请号：US16413034

申请日：2019-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Boem Park ,  Moinul Syed ,  Ju-Hee Choi

IPC: G06F12/1027 ,  G06F12/0871 ,  G06F12/1009

Abstract: Memory management unit (MMU) in an application processor responds to an access request, corresponding to inspection request, including target context and target virtual address and the inspection request is for translating the target virtual address to a first target physical address. The MMU includes context cache, translation cache, invalidation queue and address translation manager (ATM). The context cache stores contexts and context identifiers of the stored contexts, while avoiding duplicating contexts. The translation cache stores first address and first context identifiers second addresses, the first address corresponds to virtual address, the first context identifiers corresponds to first context, and the second addresses corresponds to the first address and the first context. The invalidation queue stores at least one context identifier to be invalidated, of the context identifiers stored in the translation cache. The ATM controls the context cache, the translation cache and the invalidation queue.