公开(公告)号：US11210232B2

公开(公告)日：2021-12-28

申请号：US16562011

申请日：2019-09-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Boem Park ,  Moinul Syed ,  Ju-Hee Choi

IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/0873 ,  G06F12/1027

Abstract: A processor includes a page table walk cache that stores address translation information, and a page table walker. The page table walker fetches first output addresses indicated by first indexes of a first input address by looking up the address translation information and at least a part of page tables, and compares a matching level between second indexes of a second input address and the first indexes of the first input address with a walk cache hit level obtained by looking up the page table walk cache using the second indexes.

公开(公告)号：US09990205B2

公开(公告)日：2018-06-05

申请号：US15257063

申请日：2016-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Boem Park ,  Jin-Sung Park ,  Ara Cho

IPC: G06F9/38 ,  G06F11/36 ,  G06F9/30

CPC classification number: G06F9/3865 ,  G06F9/30145 ,  G06F11/3688

Abstract: A verification method of a system on chip includes receiving a test generator and an exception handler; generating, by the test generator, a test program including an exception-causing instruction based on a test template; executing a first instruction at a first operating state as the test program is executed; stopping the execution of the test program and performing a fixed instruction sequence included in the exception handler when the exception-causing instruction is executed during the execution of the test program; and resuming the test program from a second instruction at a second operating state set after the fixed instruction sequence is performed, the second instruction corresponding to an address adjacent to an address of the exception-causing instruction.

公开(公告)号：US11216385B2

公开(公告)日：2022-01-04

申请号：US16413034

申请日：2019-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Boem Park ,  Moinul Syed ,  Ju-Hee Choi

IPC: G06F12/1027 ,  G06F12/0871 ,  G06F12/1009

Abstract: Memory management unit (MMU) in an application processor responds to an access request, corresponding to inspection request, including target context and target virtual address and the inspection request is for translating the target virtual address to a first target physical address. The MMU includes context cache, translation cache, invalidation queue and address translation manager (ATM). The context cache stores contexts and context identifiers of the stored contexts, while avoiding duplicating contexts. The translation cache stores first address and first context identifiers second addresses, the first address corresponds to virtual address, the first context identifiers corresponds to first context, and the second addresses corresponds to the first address and the first context. The invalidation queue stores at least one context identifier to be invalidated, of the context identifiers stored in the translation cache. The ATM controls the context cache, the translation cache and the invalidation queue.

公开(公告)号：US10983887B2

公开(公告)日：2021-04-20

申请号：US16705981

申请日：2019-12-06

Applicant: International Business Machines Corporation ,  Samsung Electronics Co., Ltd.

Inventor： Sung-Boem Park ,  Amir Nahir ,  Vitali Sokhin ,  Wisam Kadry ,  Jin Sung Park ,  Ara Cho

IPC: G06F11/00 ,  G06F11/22 ,  G06F11/30

Abstract: A method, apparatus and computer program product to be employed by a hardware component under validation, wherein the hardware component having a plurality of processing units each belonging to one of at least two types, such that one of the at least two types of processing units is less error-prone then a remainder of the at least two types. The method comprising: designating one of the processing units of the hardware component under validation that belongs to the less error-prone type as a manager processing unit; initiating execution of a tester program code for testing processing units, by processing units of the hardware component other than the manager processing unit; and, monitoring by the manager processing unit the status of the processing units during execution of the tester program code.

公开(公告)号：US20200151074A1

公开(公告)日：2020-05-14

申请号：US16705981

申请日：2019-12-06

Applicant: International Business Machines Corporation ,  Samsung Electronics Co., Ltd.

Inventor： Sung-Boem Park ,  Amir Nahir ,  Vitali Sokhin ,  Wisam Kadry ,  Jin Sung Park ,  Ara Cho

IPC: G06F11/22

Abstract: A method, apparatus and computer program product to be employed by a hardware component under validation, wherein the hardware component having a plurality of processing units each belonging to one of at least two types, such that one of the at least two types of processing units is less error-prone then a remainder of the at least two types. The method comprising: designating one of the processing units of the hardware component under validation that belongs to the less error-prone type as a manager processing unit; initiating execution of a tester program code for testing processing units, by processing units of the hardware component other than the manager processing unit; and, monitoring by the manager processing unit the status of the processing units during execution of the tester program code.