公开(公告)号：US20140119091A1

公开(公告)日：2014-05-01

申请号：US13960617

申请日：2013-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-Sik YOU ,  Jung-Bae LEE

IPC: G11C5/10 ,  G11C11/402

CPC classification number: G11C11/402 ,  G11C11/406 ,  G11C11/4091 ,  G11C2207/002 ,  G11C2211/4063 ,  G11C2211/4065

Abstract: A semiconductor memory device is provided which includes a sense amplifier, a bit line connected to a plurality of memory cells of a first memory block, a complementary bit line connected to a plurality of memory cells of a second memory block, a first switch configured to connect the bit line to the sense amplifier, and a second switch configured to connect the complementary bit line to the sense amplifier. The first switch is configured to electrically separate the bit line from the sense amplifier when the second memory block performs a refresh operation.

Abstract translation: 提供了一种半导体存储器件，其包括读出放大器，连接到第一存储器块的多个存储器单元的位线，连接到第二存储器块的多个存储器单元的互补位线，第一开关，被配置为 将位线连接到读出放大器，以及配置成将互补位线连接到读出放大器的第二开关。 第一开关被配置为当第二存储器块执行刷新操作时将位线与读出放大器电分离。

公开(公告)号：US20130142000A1

公开(公告)日：2013-06-06

申请号：US13754950

申请日：2013-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Cheol LEE ,  Jung-Bae LEE

IPC: G11C5/14

CPC classification number: G11C5/148 ,  G11C5/144 ,  G11C5/147 ,  G11C8/16

Abstract: Disclosed is a method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors. Control of the deep power down mode in the multi-port semiconductor memory is performed such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports.

Abstract translation: 公开了一种在多端口半导体存储器中控制深度掉电模式的方法，该多端口半导体存储器具有连接到多个处理器的多个端口。 执行多端口半导体存储器中的深度掉电模式的控制，使得根据通过多个端口中的各个端口施加的信号来确定深度掉电模式的激活/去激活。

公开(公告)号：US20140219042A1

公开(公告)日：2014-08-07

申请号：US14168793

申请日：2014-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hak-Soo YU ,  Jung-Bae LEE

IPC: G11C11/406

CPC classification number: G11C11/406 ,  G11C11/40603

Abstract: In a method of refreshing in a memory device having a plurality of pages, a candidate refresh address corresponding to a page scheduled to be refreshed after a monitoring period is generated. Whether an active command is processed for the candidate refresh address is monitored during the monitoring period. If an active command is processed for the candidate refresh address during the monitoring period, the scheduled refresh for that page is skipped. If no active command is processed for the candidate refresh address during the monitoring period, the scheduled refresh operation is performed.

Abstract translation: 在具有多个页面的存储装置中进行刷新的方法中，生成与在监视期间之后被更新的页面对应的候补刷新地址。 在监视期间监视是否处理候选刷新地址的活动命令。 如果在监视期间处理候选刷新地址的活动命令，则跳过该页面的计划刷新。 如果在监视期间没有处理候选刷新地址的活动命令，则执行预定的刷新操作。

公开(公告)号：US20140237177A1

公开(公告)日：2014-08-21

申请号：US14171343

申请日：2014-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hak-Soo YU ,  Chul-Woo PARK ,  Jung-Bae LEE

IPC: G11C11/406

CPC classification number: G11C11/40607 ,  G11C5/04 ,  G11C11/40611

Abstract: A memory module includes a master memory device and at least one slave memory device. The master memory device may generate a refresh clock signal, and perform a refresh operation in synchronization with the refresh clock signal. The slave memory device may be connected to receive the refresh clock signal, and perform a refresh operation in synchronization with the refresh clock signal.

Abstract translation: 存储器模块包括主存储器设备和至少一个从存储器设备。 主存储器件可以产生刷新时钟信号，并且与刷新时钟信号同步地执行刷新操作。 从存储器件可以被连接以接收刷新时钟信号，并且与刷新时钟信号同步地执行刷新操作。