公开(公告)号：US12230330B2

公开(公告)日：2025-02-18

申请号：US18143907

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeongwoo Lee ,  Chaehoon Kim ,  Jihwan Kim ,  Jungho Song

IPC: G11C16/24 ,  G11C16/04 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer.

公开(公告)号：US20230274783A1

公开(公告)日：2023-08-31

申请号：US18143907

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeongwoo Lee ,  Chaehoon Kim ,  Jihwan Kim ,  Jungho Song

IPC: G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C16/04

CPC classification number: G11C16/24 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  G11C16/0483 ,  H01L2924/14511 ,  H01L2225/06541 ,  H01L2224/08145 ,  H01L2924/1431

Abstract: A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer.

公开(公告)号：US11670378B2

公开(公告)日：2023-06-06

申请号：US17499533

申请日：2021-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeongwoo Lee ,  Chaehoon Kim ,  Jihwan Kim ,  Jungho Song

IPC: G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C16/04

CPC classification number: G11C16/24 ,  G11C16/0483 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer.

公开(公告)号：US20220246216A1

公开(公告)日：2022-08-04

申请号：US17499533

申请日：2021-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeongwoo Lee ,  Chaehoon Kim ,  Jihwan Kim ,  Jungho Song

IPC: G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C16/04

Abstract: A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer.