公开(公告)号：US20240412771A1

公开(公告)日：2024-12-12

申请号：US18507444

申请日：2023-11-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiryong Kim ,  Jungmyung Kang ,  Inhak Lee ,  Jaesung Choi ,  Jeonseung Kang ,  Duhwi Kim ,  Jaeyoung Kim

IPC: G11C11/4074 ,  G11C11/4072 ,  G11C11/4096

Abstract: An embedded memory device includes a retention voltage supply circuit outputting a retention voltage in response to a retention activation signal, and a plurality of array voltage supply circuits outputting corresponding array voltages to corresponding bit cells. The plurality of array voltage supply circuits respectively include an array switch providing the retention voltage as a corresponding array voltage in response to the retention activation signal, a power switch providing a power supply voltage as the corresponding array voltage in response to a power gate activation signal, and an auxiliary circuit compensating the corresponding array voltage during a write operation or a read operation.

公开(公告)号：US12300309B2

公开(公告)日：2025-05-13

申请号：US17881187

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmyung Kang ,  Hoyoung Tang ,  Inhak Lee ,  Sangyeop Baeck ,  Dongwook Seo

IPC: G11C16/04 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096

Abstract: A memory device includes a bit cell array including a plurality of bit cells connected to a first auxiliary line to which a cell power voltage is supplied; a write driver configured to apply a bit line voltage corresponding to write data to a bit line extending in a column direction of the bit cell array during a write operation; and a write auxiliary circuit connected to the first auxiliary line and a second auxiliary line extending in parallel to the first auxiliary line, and configured to lower a cell power voltage for a first bit cell spaced apart from the write driver during the write operation, wherein the cell power voltage is supplied to the first auxiliary line through the second auxiliary line, and in sequence from the first bit cell to a second bit cell adjacent to the write driver through the first auxiliary line.