公开(公告)号：US20190087044A1

公开(公告)日：2019-03-21

申请号：US16134471

申请日：2018-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunhyoung CHO ,  Bonwon KOO ,  Hyunjoon KIM ,  Haesung KIM ,  Jungyun WON

IPC: G06F3/041 ,  H01L27/32 ,  G06F3/044 ,  G06K9/00

CPC classification number: G06F3/0412 ,  G06F3/044 ,  G06K9/0002 ,  H01L27/323 ,  H01L27/3234 ,  H01L27/3244

Abstract: Provided are a pattern structure for preventing a moiré pattern from becoming visible, and a display apparatus using the same. The pattern structure includes a first element pattern including a plurality of first elements arranged regularly at a first pitch; a second element pattern including a plurality of second elements arranged regularly at a second pitch, the second element pattern being provided on the first element pattern; and a filling layer configured to fill gaps among the plurality of second elements, between adjacent ones thereof. A difference between transmittances of the second element and the filling layer is about 5% or less and thus, a moiré pattern occurring due to the overlapping of the first element pattern and the second element pattern may be prevented from becoming visible.

公开(公告)号：US20240147744A1

公开(公告)日：2024-05-02

申请号：US18472930

申请日：2023-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungyoung YUN ,  Hyeong-Ju KIM ,  Kyung Bae PARK ,  Jungyun WON ,  Bongsu KIM ,  Seongyong PARK ,  Jeong Il PARK

IPC: H10K39/34 ,  H10K59/35

CPC classification number: H10K39/34 ,  H10K59/353 ,  H10K2101/40

Abstract: A display panel may include a light emitting element including a light emitting layer and a sensor including a photosensitive layer on a substrate. The light emitting element and the sensor each may include respective portions of first and second common auxiliary layers, which may be continuous under and over the light emitting layer and the photosensitive layer. The first and second common auxiliary layers respectively may include a hole transport material and an electron transport material. The photosensitive layer may include first and second semiconductor layers close to the first and second common auxiliary layers, respectively. The first and second semiconductor layers respectively may include a p-type semiconductor and an n-type semiconductor. The second semiconductor layer may have an uneven surface facing the second common auxiliary layer and may have an average roughness (Rq) of greater than or equal to about 5 nm.