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公开(公告)号:US12167598B2
公开(公告)日:2024-12-10
申请号:US17703130
申请日:2022-03-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kanamori Kohji , Jeehoon Han
IPC: H10B43/27 , H01L23/528 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/48 , H10B43/10 , H10B43/35 , H10B43/40
Abstract: Disclosed are three-dimensional semiconductor memory devices, methods of manufacturing the same, and electronic systems including the same. The device includes a peripheral circuit structure on a substrate, and a cell array structure including a stack structure that includes gate electrodes on the peripheral circuit structure, a first source conductive pattern on the stack structure, and vertical channel structures in vertical channel holes that penetrate the stack structure and the first source conductive pattern. The vertical channel structure includes a data storage pattern on a sidewall of the vertical channel hole, a vertical semiconductor pattern on the data storage pattern, and a second source conductive pattern on the vertical semiconductor pattern and surrounded by the data storage pattern. A thickness of the data storage pattern between the first source conductive pattern and the second source conductive pattern is greater than it is between the stack structure and the vertical semiconductor pattern.
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公开(公告)号:US20250056805A1
公开(公告)日:2025-02-13
申请号:US18932884
申请日:2024-10-31
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kanamori Kohji , Jeehoon Han
IPC: H10B43/27 , H01L23/528 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/48 , H10B43/10 , H10B43/35 , H10B43/40
Abstract: Disclosed are three-dimensional semiconductor memory devices, methods of manufacturing the same, and electronic systems including the same. The device includes a peripheral circuit structure on a substrate, and a cell array structure including a stack structure that includes gate electrodes on the peripheral circuit structure, a first source conductive pattern on the stack structure, and vertical channel structures in vertical channel holes that penetrate the stack structure and the first source conductive pattern. The vertical channel structure includes a data storage pattern on a sidewall of the vertical channel hole, a vertical semiconductor pattern on the data storage pattern, and a second source conductive pattern on the vertical semiconductor pattern and surrounded by the data storage pattern. A thickness of the data storage pattern between the first source conductive pattern and the second source conductive pattern is greater than it is between the stack structure and the vertical semiconductor pattern.
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公开(公告)号:US20230134878A1
公开(公告)日:2023-05-04
申请号:US17842878
申请日:2022-06-17
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seung Yoon Kim , Kanamori Kohji , Jeehoon Han
IPC: H01L27/11575 , H01L23/535 , H01L27/11582 , H01L27/11573
Abstract: A three-dimensional semiconductor memory device includes a substrate, and a stack structure on the substrate. The stack structure includes first blocks that extend in a first direction and are arranged in a second direction intersecting the first direction, and a second block that is between the first blocks; separation structures that extend in the first direction and are arranged in the second direction between the first blocks and between the first and second blocks; vertical channel structures that penetrate the first blocks and contact the substrate; and through-via structures that penetrate the second block and the substrate. A width of each of the first blocks in the second direction is equal to a width of the second block in the second direction.
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公开(公告)号:US20230028532A1
公开(公告)日:2023-01-26
申请号:US17703130
申请日:2022-03-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kanamori Kohji , Jeehoon Han
IPC: H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11543 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L23/528
Abstract: Disclosed are three-dimensional semiconductor memory devices, methods of manufacturing the same, and electronic systems including the same. The device includes a peripheral circuit structure on a substrate, and a cell array structure including a stack structure that includes gate electrodes on the peripheral circuit structure, a first source conductive pattern on the stack structure, and vertical channel structures in vertical channel holes that penetrate the stack structure and the first source conductive pattern. The vertical channel structure includes a data storage pattern on a sidewall of the vertical channel hole, a vertical semiconductor pattern on the data storage pattern, and a second source conductive pattern on the vertical semiconductor pattern and surrounded by the data storage pattern. A thickness of the data storage pattern between the first source conductive pattern and the second source conductive pattern is greater than it is between the stack structure and the vertical semiconductor pattern.
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