公开(公告)号：US08576650B2

公开(公告)日：2013-11-05

申请号：US13790306

申请日：2013-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Young Oh ,  Seung-Jun Bae ,  Kwnag-Il Park

IPC: G11C7/02

CPC classification number: G11C7/10 ,  G11C7/02

Abstract: A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line.