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公开(公告)号：US10943630B2
公开(公告)日：2021-03-09
申请号：US16731769
申请日：2019-12-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hye-Ran Kim , Seong-Hwan Jeon , Tae-Young Oh
IPC: G06F1/12 , G11C7/22 , G11C11/4093 , G11C11/4076 , G11C7/10 , G06F13/16
Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.
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公开(公告)号：US10553264B2
公开(公告)日：2020-02-04
申请号：US15723532
申请日：2017-10-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hye-Ran Kim , Seong-Hwan Jeon , Tae-Young Oh
Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.
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公开(公告)号：US09959918B2
公开(公告)日：2018-05-01
申请号：US15298491
申请日：2016-10-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hye-Ran Kim , Tae-Young Oh
CPC classification number: G11C8/10 , G11C7/1072 , G11C7/222 , G11C8/18 , G11C29/023 , G11C29/028 , G11C2207/2254
Abstract: An operating method of a memory device includes entering into a command bus training mode, generating a plurality of internal clock signals by dividing a received clock signal, generating a plurality of internal chip selection signals by latching a received chip selection signal according to the plurality of internal clock signals, generating a second command/address signal by encoding a received first command/address signal based on the plurality of internal chip selection signals, and outputting the second command/address signal.
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公开(公告)号：US09825631B1
公开(公告)日：2017-11-21
申请号：US15390851
申请日：2016-12-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seok-Jin Cho , Tae-Young Oh
IPC: H03K17/16 , H03K19/003 , H03K19/00 , G11C5/14 , G11C7/10
CPC classification number: H03K19/0005 , G11C5/147 , G11C7/10 , G11C7/1057 , G11C7/1066 , G11C7/1084 , G11C7/1093 , G11C7/227 , G11C11/4093 , G11C29/021 , G11C29/022 , G11C29/025 , G11C29/028 , G11C2207/2254
Abstract: An impedance calibration circuit includes a first code generator, a first code storing circuit, a second code generator and a second code storing circuit. The first code generator generates a pull-up control code obtained from a result of comparing a target output high level (VOH) voltage with a first voltage of a first node. The first code storing circuit stores the pull-up control code when the target VOH voltage becomes the same as the first voltage. The second code generator generates a pull-down control code obtained from a result of comparing the VOH voltage with a second voltage of a second node. The second storing circuit stores the pull-down control code when the target VOH voltage becomes the same as the second voltage. The first code storing circuit and the second code storing circuit store pull-up control code and pull-down control code pairs respectively.
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公开(公告)号：US12057193B2
公开(公告)日：2024-08-06
申请号：US18111925
申请日：2023-02-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hye-Ran Kim , Seong-Hwan Jeon , Tae-Young Oh
IPC: G06F1/12 , G06F13/16 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4093
CPC classification number: G11C7/222 , G06F1/12 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C11/4076 , G11C11/4093 , G11C2207/2254
Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.
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Patent Agency Ranking
公开(公告)号：US11615825B2
公开(公告)日：2023-03-28
申请号：US17588566
申请日：2022-01-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hye-Ran Kim , Seong-Hwan Jeon , Tae-Young Oh
IPC: G06F1/12 , G11C7/22 , G11C11/4093 , G11C11/4076 , G11C7/10 , G06F13/16
Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.
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公开(公告)号：US09973323B2
公开(公告)日：2018-05-15
申请号：US14614324
申请日：2015-02-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Il-Pyo Hong , Tae-Young Oh , Young-Sang Hong
Abstract: An electronic device and method for providing a communication service are provided. The method of operating an electronic device includes: receiving a first signal transmitted through a first band and a second signal transmitted through a second band; determining a communication mode of the electronic device for processing the first signal and the second signal based on device information or environment information of the electronic device; and processing the first signal and the second signal using at least one of a first modem or a second modem functionally connected to the electronic device based on the communication mode, wherein the processing of the first signal and the second signal includes: processing, when the communication mode is a first mode, the first signal in the first modem and the second signal in the second modem; and processing, when the communication mode is a second mode, the first signal and the second signal in the first modem.
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公开(公告)号：US09532397B2
公开(公告)日：2016-12-27
申请号：US14633483
申请日：2015-02-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Doo-Hwan Lee , Tae-Young Oh , Il-Pyo Hong , Seong-Won Son , Tae-Sin Song
CPC classification number: H04W88/06 , H04B7/06 , H04W36/0022
Abstract: An apparatus and method for providing an LTE service in an electronic device. The method includes: transmitting or receiving a voice signal through a first antenna and a data signal through a second antenna when the electronic device provides a multi-communication service. At least one switch connects at least one antenna and at least one communication interface with each other. When the electronic device provides a single communication service, transmitting or receiving a data signal or a voice signal through the first antenna, using the at least one switch.
Abstract translation: 一种用于在电子设备中提供LTE服务的装置和方法。 该方法包括：当电子设备提供多通信服务时，通过第一天线通过第二天线发送或接收语音信号和数据信号。 至少一个开关将至少一个天线和至少一个通信接口彼此连接起来。 当电子设备提供单个通信服务时，使用至少一个开关通过第一天线发送或接收数据信号或语音信号。
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公开(公告)号：US20150222411A1
公开(公告)日：2015-08-06
申请号：US14614324
申请日：2015-02-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Il-Pyo Hong , Tae-Young Oh , Young-Sang Hong
Abstract: An electronic device and method for providing a communication service are provided. The method of operating an electronic device includes: receiving a first signal transmitted through a first band and a second signal transmitted through a second band; determining a communication mode of the electronic device for processing the first signal and the second signal based on device information or environment information of the electronic device; and processing the first signal and the second signal using at least one of a first modem or a second modem functionally connected to the electronic device based on the communication mode, wherein the processing of the first signal and the second signal includes: processing, when the communication mode is a first mode, the first signal in the first modem and the second signal in the second modem; and processing, when the communication mode is a second mode, the first signal and the second signal in the first modem.
Abstract translation: 提供了一种用于提供通信服务的电子设备和方法。 操作电子设备的方法包括：接收通过第一频带发送的第一信号和通过第二频带发送的第二信号; 基于所述电子设备的设备信息或环境信息确定用于处理所述第一信号和所述第二信号的所述电子设备的通信模式; 以及使用基于所述通信模式功能地连接到所述电子设备的第一调制解调器或第二调制解调器或第二调制解调器中的至少一个来处理所述第一信号和所述第二信号，其中所述第一信号和所述第二信号的处理包括： 通信模式是第一模式，第一调制解调器中的第一信号和第二调制解调器中的第二信号; 以及当所述通信模式是第二模式时，在所述第一调制解调器中处理所述第一信号和所述第二信号。
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公开(公告)号：US08576650B2
公开(公告)日：2013-11-05
申请号：US13790306
申请日：2013-03-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tae-Young Oh , Seung-Jun Bae , Kwnag-Il Park
IPC: G11C7/02
Abstract: A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line.
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