公开(公告)号：US20210313427A1

公开(公告)日：2021-10-07

申请号：US17085467

申请日：2020-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil KIM ,  Kyengmun KANG ,  Juyon SUH ,  Hyeeun HONG

IPC: H01L29/10 ,  H01L25/07 ,  H01L23/00

Abstract: A semiconductor device, includes: gate electrodes spaced apart from each other and on a substrate; channel structures penetrating the gate electrodes, each of channel structures including a channel layer, a gate dielectric layer between the channel layer and the gate electrodes, a channel insulating layer filling between the channel layers, a channel pad on the channel insulating layer; and separation regions penetrating the gate electrodes, and spaced apart from each other, wherein the gate dielectric layer extends upwardly, further than the channel layer upwardly such that a portion of an inner side surface of the gate dielectric layer contacts the channel pad, the channel pad includes a lower pad on an upper end of the channel layer and the inner side surface of the gate dielectric layer, and having a first recess between the inner side surfaces of the gate dielectric layer; and an upper pad having a first portion in the first recess and a second portion extending from the first portion in a direction, parallel to an upper surface of the substrate on the first portion.

公开(公告)号：US20220278201A1

公开(公告)日：2022-09-01

申请号：US17749719

申请日：2022-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil KIM ,  Kyengmun KANG ,  Juyon SUH ,  Hyeeun HONG

IPC: H01L29/10 ,  H01L25/07 ,  H01L23/00

Abstract: A semiconductor device, includes: gate electrodes spaced apart from each other and on a substrate; channel structures penetrating the gate electrodes, each of channel structures including a channel layer, a gate dielectric layer between the channel layer and the gate electrodes, a channel insulating layer filling between the channel layers, a channel pad on the channel insulating layer; and separation regions penetrating the gate electrodes, and spaced apart from each other, wherein the gate dielectric layer extends upwardly, further than the channel layer upwardly such that a portion of an inner side surface of the gate dielectric layer contacts the channel pad, the channel pad includes a lower pad on an upper end of the channel layer and the inner side surface of the gate dielectric layer, and having a first recess between the inner side surfaces of the gate dielectric layer; and an upper pad having a first portion in the first recess and a second portion extending from the first portion in a direction, parallel to an upper surface of the substrate on the first portion.