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公开(公告)号：US20190181226A1
公开(公告)日：2019-06-13
申请号：US16186915
申请日：2018-11-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Hoon CHOI , Dongkyum KIM , Sunggil KIM , Seulye KIM , Sangsoo LEE , Hyeeun HONG
IPC: H01L29/10 , H01L27/11556 , H01L27/11582 , H01L29/423 , H01L27/11526 , H01L27/11573
Abstract: A three-dimensional semiconductor memory device includes an electrode structure including electrodes vertically stacked on a semiconductor layer, a vertical semiconductor pattern penetrating the electrode structure and connected to the semiconductor layer, and a vertical insulating pattern between the electrode structure and the vertical semiconductor pattern. The vertical insulating pattern includes a sidewall portion on a sidewall of the electrode structure, and a protrusion extending from the sidewall portion along a portion of a top surface of the semiconductor layer. The vertical semiconductor pattern includes a vertical channel portion having a first thickness and extending along the sidewall portion of the vertical insulating pattern, and a contact portion extending from the vertical channel portion and conformally along the protrusion of the vertical insulating pattern and the top surface of the semiconductor layer. The contact portion has a second thickness greater than the first thickness.
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公开(公告)号：US20180315770A1
公开(公告)日：2018-11-01
申请号：US15864410
申请日：2018-01-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Hoon CHOI , Sunggil KIM , Seulye KIM , HongSuk KIM , Phil Ouk NAM , Jaeyoung AHN
IPC: H01L27/11582 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L29/04 , H01L29/792 , H01L29/423
Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.
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公开(公告)号：US20210313427A1
公开(公告)日：2021-10-07
申请号：US17085467
申请日：2020-10-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sunggil KIM , Kyengmun KANG , Juyon SUH , Hyeeun HONG
Abstract: A semiconductor device, includes: gate electrodes spaced apart from each other and on a substrate; channel structures penetrating the gate electrodes, each of channel structures including a channel layer, a gate dielectric layer between the channel layer and the gate electrodes, a channel insulating layer filling between the channel layers, a channel pad on the channel insulating layer; and separation regions penetrating the gate electrodes, and spaced apart from each other, wherein the gate dielectric layer extends upwardly, further than the channel layer upwardly such that a portion of an inner side surface of the gate dielectric layer contacts the channel pad, the channel pad includes a lower pad on an upper end of the channel layer and the inner side surface of the gate dielectric layer, and having a first recess between the inner side surfaces of the gate dielectric layer; and an upper pad having a first portion in the first recess and a second portion extending from the first portion in a direction, parallel to an upper surface of the substrate on the first portion.
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公开(公告)号：US20140106537A1
公开(公告)日：2014-04-17
申请号：US14053913
申请日：2013-10-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-Hwan KIM , Sunggil KIM , HungSuk KIM , Guk-Hyon YON , Hunhyeong LIM
IPC: H01L21/762
CPC classification number: H01L21/76224 , H01L21/28273 , H01L21/32155 , H01L21/764 , H01L27/11524
Abstract: Methods of manufacturing a semiconductor device are provided. The method includes forming a poly-silicon layer doped with first p-type dopants on a substrate, etching the poly-silicon layer and the substrate to form a poly-silicon pattern and a trench, forming device isolation pattern covering a lower sidewall of the poly-silicon pattern in the trench, thermally treating the poly-silicon pattern in a gas including second p-type dopants, forming a dielectric layer and a conductive layer on the thermally treated poly-silicon pattern and the device isolation pattern, etching the conductive layer, the dielectric layer, and the thermally treated poly-silicon pattern to form a control gate, a dielectric pattern, and a floating gate respectively.
Abstract translation: 提供制造半导体器件的方法。 该方法包括在衬底上形成掺杂有第一p型掺杂剂的多晶硅层，蚀刻多晶硅层和衬底以形成多晶硅图案和沟槽，从而形成覆盖层的下侧壁的器件隔离图案 沟槽中的多晶硅图案，在包括第二p型掺杂剂的气体中热处理多晶硅图案，在热处理的多晶硅图案和器件隔离图案上形成电介质层和导电层，蚀刻导电 层，电介质层和热处理的多晶硅图案，以分别形成控制栅极，电介质图案和浮置栅极。
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公开(公告)号：US20230328988A1
公开(公告)日：2023-10-12
申请号：US18166854
申请日：2023-02-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sunggil KIM , Siyeong YANG
IPC: H10B43/27
CPC classification number: H10B43/27
Abstract: A vertical semiconductor device may include a substrate, a pattern structure on the substrate, and a channel structure in a channel hole passing through the pattern structure. The pattern structure may include insulation patterns and gate structures alternately stacked in a vertical direction perpendicular to an upper surface of the substrate. The channel structure may extend in the vertical direction. The channel structure may include a data storage structure on an inner surface of the channel hole, a channel contacting the data storage structure, a lower pattern on the channel positioned at a lower portion of the channel hole, and a filling insulation pattern on the channel and the lower pattern. The channel may have a cylindrical shape. The lower pattern may include an oxide including silicon and germanium.
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Patent Agency Ranking
公开(公告)号：US20220344368A1
公开(公告)日：2022-10-27
申请号：US17668889
申请日：2022-02-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sangmin KANG , Sunggil KIM , Jeeseung LIM
IPC: H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11526 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573
Abstract: Disclosed are semiconductor devices and electronic systems including the same. The semiconductor device includes a stack structure including electrodes vertically stacked on a semiconductor layer, a source semiconductor pattern between the semiconductor layer and the stack structure, a support semiconductor pattern between the stack structure and the source semiconductor pattern, and a vertical structure penetrating the stack structure, the support semiconductor pattern, and the source semiconductor pattern. The vertical structure includes a vertical channel pattern in which a part of a sidewall is in contact with the source semiconductor pattern. The vertical channel pattern includes an upper portion adjacent to the stack structure, a lower portion adjacent to the source semiconductor pattern, and a middle portion adjacent to the support semiconductor pattern. The upper portion has a first diameter. The lower portion has a second diameter. The middle portion has a third diameter less than the first and second diameters.
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公开(公告)号：US20220139956A1
公开(公告)日：2022-05-05
申请号：US17578965
申请日：2022-01-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Hoon CHOI , Sunggil KIM , Seulye KIM , HongSuk KIM , Phil Ouk NAM , Jaeyoung AHN
IPC: H01L27/11582 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L29/792 , H01L29/423 , H01L29/04 , H01L27/11565 , H01L21/02 , H01L21/306 , H01L21/3065 , H01L27/11524 , H01L27/11556
Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.
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公开(公告)号：US20240324218A1
公开(公告)日：2024-09-26
申请号：US18601245
申请日：2024-03-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jehong OH , Younghwan JO , Seulye KIM , Moohyun KIM , Sunggil KIM
Abstract: A non-volatile memory device includes a substrate including a memory cell region and a connection region, a mold structure including a plurality of gate electrodes sequentially stacked on the memory cell region and stacked stepwise on the connection region, and a plurality of mold insulating layers alternately stacked with the plurality of gate electrodes, a channel hole vertically passing through the mold structure on the memory cell region, and a channel structure disposed in the channel hole, wherein the channel structure includes a gate insulating layer, a channel layer, and a buried insulating layer sequentially disposed in the channel hole, and the channel layer includes a grain having a size of about 20 nm to about 17 μm.
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公开(公告)号：US20240224532A1
公开(公告)日：2024-07-04
申请号：US18462390
申请日：2023-09-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jumi BAK , Eun- Young LEE , Sunggil KIM
IPC: H10B43/40 , G11C16/04 , H01L25/065 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/41 , H10B43/10 , H10B43/27 , H10B43/35 , H10B80/00
CPC classification number: H10B43/40 , G11C16/0483 , H01L25/0652 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/41 , H10B43/10 , H10B43/27 , H10B43/35 , H10B80/00 , H01L2225/06506
Abstract: A semiconductor device includes a semiconductor substrate, a peripheral circuit structure including peripheral circuits integrated on the semiconductor substrate and first bonding pads connected to the peripheral circuits, and a cell array structure including second bonding pads bonded to the first bonding pads. The cell array structure includes separation structures extending in a first direction, a stack disposed between the separation structures, a source conductive pattern disposed on the stack, vertical structures penetrating the stack and connected to the source conductive pattern, and reflection structures, which are vertically spaced apart from the source conductive pattern and are overlapped with the separation structures. The stack includes interlayer insulating layers and gate patterns, which are vertically and alternately stacked on top of one another.
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公开(公告)号：US20240206174A1
公开(公告)日：2024-06-20
申请号：US18498696
申请日：2023-10-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seulye KIM , Sunhwa LIM , Moohyun KIM , Sunggil KIM , Yunji PARK , Younghwan JO
CPC classification number: H10B43/27 , H01L25/0652 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/35 , H10B80/00 , H01L2225/06524
Abstract: A semiconductor device may include a gate stack including insulating and conductive patterns, which are alternately stacked on top of each other, a memory channel structure penetrating the gate stack, a selection line structure on the gate stack, and a selection channel structure penetrating the selection line structure. The selection channel structure may include a selection channel layer, which is electrically connected to the memory channel layer, and a selection insulating structure, which encloses the selection channel layer. The selection channel layer may include a connecting portion on the memory channel structure and a pillar portion on the connecting portion, and an average size of grains in the connecting portion may be less than an average size of grains in the pillar portion.
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