公开(公告)号：US20250120162A1

公开(公告)日：2025-04-10

申请号：US18989196

申请日：2024-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： HWI CHAN JUN ,  MIN GYU KIM

IPC: H10D84/01 ,  H10D84/03

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the same are provided. The methods may include forming a lower structure on a substrate. The lower structure may include first and second VFETs, a preliminary isolation structure between the first and second VFETs, and a gate liner on opposing sides of the preliminary isolation structure and between the preliminary isolation structure and the substrate. Each of the first and second VFETs may include a bottom source/drain region, a channel region and a top source/drain region sequentially stacked, and a gate structure on a side surface of the channel region. The preliminary isolation structure may include a sacrificial layer and a gap capping layer sequentially stacked. The methods may also include forming a top capping layer on the lower structure and then forming a cavity between the first and second VFETs by removing the sacrificial layer.

公开(公告)号：US20240170338A1

公开(公告)日：2024-05-23

申请号：US18418795

申请日：2024-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： HWI CHAN JUN ,  MIN GYU KIM

IPC: H01L21/8234

CPC classification number: H01L21/823487 ,  H01L21/823437 ,  H01L21/823481

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the same are provided. The methods may include forming a lower structure on a substrate. The lower structure may include first and second VFETs, a preliminary isolation structure between the first and second VFETs, and a gate liner on opposing sides of the preliminary isolation structure and between the preliminary isolation structure and the substrate. Each of the first and second VFETs may include a bottom source/drain region, a channel region and a top source/drain region sequentially stacked, and a gate structure on a side surface of the channel region. The preliminary isolation structure may include a sacrificial layer and a gap capping layer sequentially stacked. The methods may also include forming a top capping layer on the lower structure and then forming a cavity between the first and second VFETs by removing the sacrificial layer.

公开(公告)号：US20210242091A1

公开(公告)日：2021-08-05

申请号：US17035857

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： HWI CHAN JUN ,  MIN GYU KIM

IPC: H01L21/8234

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the same are provided. The methods may include forming a lower structure on a substrate. The lower structure may include first and second VFETs, a preliminary isolation structure between the first and second VFETs, and a gate liner on opposing sides of the preliminary isolation structure and between the preliminary isolation structure and the substrate. Each of the first and second VFETs may include a bottom source/drain region, a channel region and a top source/drain region sequentially stacked, and a gate structure on a side surface of the channel region. The preliminary isolation structure may include a sacrificial layer and a gap capping layer sequentially stacked. The methods may also include forming a top capping layer on the lower structure and then forming a cavity between the first and second VFETs by removing the sacrificial layer.

公开(公告)号：US20200150795A1

公开(公告)日：2020-05-14

申请号：US16549714

申请日：2019-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YONG JIN PARK ,  MIN GYU KIM ,  SUN KWON KIM ,  JONG BIN MOON ,  YOUNG KIL CHOI ,  YOON KYUNG CHOI

IPC: G06F3/044 ,  G01R27/26

Abstract: A method for acquiring capacitance of a capacitive touch panel includes acquiring a selected capacitance value at a selected point among a plurality of points at which a plurality of capacitances are present, in the capacitive touch panel, determining the selected capacitance value as a reference capacitance value, and performing a multi-driving using a balanced code, and acquiring a capacitance value from at least one point among the plurality of points using the reference capacitance value.

公开(公告)号：US20190213374A1

公开(公告)日：2019-07-11

申请号：US16058661

申请日：2018-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YONGIL KWON ,  MIN GYU KIM ,  MOONSUK JEONG

IPC: G06K9/00 ,  G06F3/041 ,  G06F21/32

CPC classification number: G06K9/0002 ,  G06F3/0412 ,  G06F21/32 ,  G06K9/00087

Abstract: A fingerprint sensor includes a fingerprint pixel that detects a fingerprint capacitance of a user fingerprint based on a first voltage and outputs fingerprint information corresponding to the detected fingerprint capacitance through a first node. A voltage conversion circuit converts the fingerprint information received through the first node to a signal, which is based on a second voltage lower than the first voltage, and outputs the converted signal. An analog circuit outputs an output signal based on the converted signal by using the second voltage.