公开(公告)号：US20240170338A1

公开(公告)日：2024-05-23

申请号：US18418795

申请日：2024-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： HWI CHAN JUN ,  MIN GYU KIM

IPC: H01L21/8234

CPC classification number: H01L21/823487 ,  H01L21/823437 ,  H01L21/823481

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the same are provided. The methods may include forming a lower structure on a substrate. The lower structure may include first and second VFETs, a preliminary isolation structure between the first and second VFETs, and a gate liner on opposing sides of the preliminary isolation structure and between the preliminary isolation structure and the substrate. Each of the first and second VFETs may include a bottom source/drain region, a channel region and a top source/drain region sequentially stacked, and a gate structure on a side surface of the channel region. The preliminary isolation structure may include a sacrificial layer and a gap capping layer sequentially stacked. The methods may also include forming a top capping layer on the lower structure and then forming a cavity between the first and second VFETs by removing the sacrificial layer.

公开(公告)号：US20210242091A1

公开(公告)日：2021-08-05

申请号：US17035857

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： HWI CHAN JUN ,  MIN GYU KIM

IPC: H01L21/8234

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the same are provided. The methods may include forming a lower structure on a substrate. The lower structure may include first and second VFETs, a preliminary isolation structure between the first and second VFETs, and a gate liner on opposing sides of the preliminary isolation structure and between the preliminary isolation structure and the substrate. Each of the first and second VFETs may include a bottom source/drain region, a channel region and a top source/drain region sequentially stacked, and a gate structure on a side surface of the channel region. The preliminary isolation structure may include a sacrificial layer and a gap capping layer sequentially stacked. The methods may also include forming a top capping layer on the lower structure and then forming a cavity between the first and second VFETs by removing the sacrificial layer.

公开(公告)号：US20190131171A1

公开(公告)日：2019-05-02

申请号：US15959783

申请日：2018-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Chan Gwak ,  HWI CHAN JUN ,  HEON JONG SHIN ,  SO RA YOU ,  SANG HYUN LEE ,  IN CHAN HWANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66 ,  H01L29/417

Abstract: A semiconductor device includes a plurality of active regions spaced apart from each other and extending linearly in parallel on a substrate. A gate electrode crosses the plurality of active regions, and respective drain regions are on and/or in respective ones of the active regions on a first side of the gate electrode and respective source regions are on and/or in respective ones of the active regions on a second side of the gate electrode. A drain plug is disposed on the drain regions and a source plug is disposed on the source regions. A gate plug is disposed on the gate electrode between the drain plug and the source plug such that a straight line passing through a center of the drain plug and a center of the source plug intersects the gate plug.

公开(公告)号：US20250120162A1

公开(公告)日：2025-04-10

申请号：US18989196

申请日：2024-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： HWI CHAN JUN ,  MIN GYU KIM

IPC: H10D84/01 ,  H10D84/03

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the same are provided. The methods may include forming a lower structure on a substrate. The lower structure may include first and second VFETs, a preliminary isolation structure between the first and second VFETs, and a gate liner on opposing sides of the preliminary isolation structure and between the preliminary isolation structure and the substrate. Each of the first and second VFETs may include a bottom source/drain region, a channel region and a top source/drain region sequentially stacked, and a gate structure on a side surface of the channel region. The preliminary isolation structure may include a sacrificial layer and a gap capping layer sequentially stacked. The methods may also include forming a top capping layer on the lower structure and then forming a cavity between the first and second VFETs by removing the sacrificial layer.

公开(公告)号：US20190057907A1

公开(公告)日：2019-02-21

申请号：US16169326

申请日：2018-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HWI CHAN JUN ,  Chang Hwa Kim ,  Dae Won Ha

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L23/522 ,  H01L27/088

Abstract: A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region. First and second source/drain regions and first and second gate electrodes are on the lower active region. The first and second source/drain regions are adjacent to each other. First and second gate capping patterns are on the first and second gate electrodes, respectively. First and second contact structures are on the first and second source/drain regions, respectively. A lower insulating pattern is between the first and second source/drain regions. An upper insulating pattern is between the first and second contact structures. Silicon oxide has etching selectivity with respect to an insulating material which the upper insulating pattern, the first gate capping pattern, and the second gate capping pattern are formed of.

公开(公告)号：US20210375692A1

公开(公告)日：2021-12-02

申请号：US17398623

申请日：2021-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HWI CHAN JUN ,  Chang Hwa Kim ,  Dae Won Ha

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L23/522 ,  H01L27/088

Abstract: A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region. First and second source/drain regions and first and second gate electrodes are on the lower active region. The first and second source/drain regions are adjacent to each other. First and second gate capping patterns are on the first and second gate electrodes, respectively. First and second contact structures are on the first and second source/drain regions, respectively. A lower insulating pattern is between the first and second source/drain regions. An upper insulating pattern is between the first and second contact structures. Silicon oxide has etching selectivity with respect to an insulating material which the upper insulating pattern, the first gate capping pattern, and the second gate capping pattern are formed of.

公开(公告)号：US20180047634A1

公开(公告)日：2018-02-15

申请号：US15449302

申请日：2017-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HWI CHAN JUN ,  CHANG HWA KIM ,  DAE WON HA

IPC: H01L21/8234 ,  H01L23/522 ,  H01L27/088

CPC classification number: H01L21/823475 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region. First and second source/drain regions and first and second gate electrodes are on the lower active region. The first and second source/drain regions are adjacent to each other. First and second gate capping patterns are on the first and second gate electrodes, respectively. First and second contact structures are on the first and second source/drain regions, respectively. A lower insulating pattern is between the first and second source/drain regions. An upper insulating pattern is between the first and second contact structures. Silicon oxide has etching selectivity with respect to an insulating material which the upper insulating pattern, the first gate capping pattern, and the second gate capping pattern are formed of.