公开(公告)号：US20240220700A1

公开(公告)日：2024-07-04

申请号：US18210836

申请日：2023-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangwoo Heo ,  Majd Kuteifan ,  Mindy Lee ,  SOOYONG LEE ,  JEEYONG LEE

IPC: G06F30/392

CPC classification number: G06F30/392 ,  G06F2119/02

Abstract: Provided is a process model generating method including: obtaining a target layout for a process of a semiconductor device and a plurality of sublayers representing a substructure of the semiconductor device; determining a lateral feature and a vertical feature of the target layout; and generating a correction model for the target layout based on the lateral feature and the vertical feature.