公开(公告)号：US20230123297A1

公开(公告)日：2023-04-20

申请号：US17863697

申请日：2022-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungsoo Kim ,  Sangwan Nam ,  MinJae Seo ,  Bongsoon Lim

IPC: H01L27/11575 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582

Abstract: A memory device includes a first cell array region and a second cell array region separated by a separation region, each including at least one memory block having a plurality of gate electrode layers stacked in a first direction. The gate electrode layers include an upper select electrode layer including a plurality of string select lines, and a first electrode layer including a plurality of first word lines arranged below the string select lines. The first word lines include a first connection line to connect first end portions of the first word lines positioned on the opposite side of the separation region to each other and a plurality of second connection lines to connect some of second end portions of the plurality of first word lines adjacent to the separation region to each other, wherein each of the second connection lines is shorter than the first connection line.