-
公开(公告)号：US20180300131A1
公开(公告)日：2018-10-18
申请号：US15633746
申请日：2017-06-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： David C. TANNENBAUM , Srinivasan S. IYER , Mitchell K. ALSUP
CPC classification number: G06F9/3009 , G06F9/3001 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30098 , G06F9/3012 , G06F9/3824 , G06F9/3828 , G06F9/3851 , G06F9/3867 , G06F9/3887 , G06F9/3891 , G06F9/46 , G06T1/20 , G06T1/60
Abstract: A graphics processing unit may include a register file memory, a processing element (PE) and a load-store unit (LSU). The register file memory includes a plurality of registers. The PE is coupled to the register file memory and processes at least one thread of a vector of threads of a graphical application. Each thread in the vector of threads are processed in a non-stalling manner. The PE stores data in a first predetermined set of the plurality of registers in the register file memory that has been generated by processing the at least one thread and that is to be routed to a first stallable logic unit that is external to the PE. The LSU is coupled to the register file memory, and the LSU accesses the data in the first predetermined set of the plurality of registers and routes to the first stallable logic unit.
-
公开(公告)号：US20180196771A1
公开(公告)日：2018-07-12
申请号：US15713585
申请日：2017-09-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： David C. TANNENBAUM , Mitchell K. ALSUP , Srinivasan S. IYER
IPC: G06F13/366 , G06F13/40
CPC classification number: G06F13/366 , G06F13/4031
Abstract: According to one general aspect, an apparatus may include a network of node circuits and a central arbiter circuit. The network of node circuits is within an integrated circuit, wherein the network includes a plurality of segments. The central arbiter circuit may be configured to schedule a routing of a message between a pair of node circuits in the network, wherein the routing includes a guaranteed latency between the pair of node circuits.
-
Search Results
2
records
(took 0.018 seconds)
