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公开(公告)号：US20220148122A1
公开(公告)日：2022-05-12
申请号：US17110284
申请日：2020-12-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： David C. TANNENBAUM , Keshavan VARADARAJAN , Veynu NARASIMAN
Abstract: A binning subsystem of a GPU includes a storage subsystem, a shader core to output first data via a first path, a selector to receive the first data via the first path, and to receive second data from the storage subsystem via a second path. The storage subsystem includes a binner unit and a control logic unit. The control logic unit causes the selector to transfer the first data or the second data to the binner unit. The binner unit may transfer binner output data to the shader core via a third path. The binner unit may transfer the binner output data to one or more subsequent stages of a graphics pipeline via a fourth path. The binner unit may transfer the binner output data to the storage subsystem via a fifth path. The control logic unit may control the binner unit such that the binner unit can be used for general purpose computation.
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公开(公告)号：US20220036632A1
公开(公告)日：2022-02-03
申请号：US17187729
申请日：2021-02-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Raun M. KRISCH , David C. TANNENBAUM , Moumine BALLO , Keshavan VARADARAJAN
Abstract: A GPU includes one or more post-processing controllers, and a 3D graphics pipeline including a post-processing shader stage following a pixel shader stage. The one or more post-processing controllers may synchronize an execution of one or more post-processing stages including the post-processing shader stage. The 3D pipeline may include one or more pixel shaders, one or more tile buffers, and a direct communication link between the post-processing shader stage and the one or more tile buffers. The one or more post-processing controllers may synchronize communication between the one or more post-processing shaders and the one or more tile buffers.
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公开(公告)号：US20220206737A1
公开(公告)日：2022-06-30
申请号：US17209209
申请日：2021-03-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Gabriel T. DAGANI , David C. TANNENBAUM , Christopher P. FRASCATI , Michael PHILLIP
Abstract: A system and method is disclosed that allows multiple casting devices to work together to populate a large display screen according to the subject matter disclosed herein. The system includes a receiving device that includes two or more screen-cast receivers and a controller. Each screen-cast receiver receives from a corresponding casting device at least a portion of a frame of original content of the corresponding casting device generated in a native resolution of the corresponding casting device. The controller synchronizes each received portion of the frame of the original content of the corresponding casting device to form a video output signal that comprises a combination of each received portion, in addition to any internally generated content derived by the receiving display. A casting device may be a smartphone, a tablet, or a computing device, such as a laptop computer.
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公开(公告)号：US20180164372A1
公开(公告)日：2018-06-14
申请号：US15464334
申请日：2017-03-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Lawrence H. RUBIN , David C. TANNENBAUM
IPC: G01R31/317 , G01R31/3177
CPC classification number: G01R31/31705 , G06F11/00
Abstract: According to one general aspect, an apparatus may include a plurality of performance and debug monitoring circuits (PDMCs). Each performance and debug monitoring circuit (PDMC) may include an input stage, a combinatorial stage, and a counter. The input stage may be configured to receive a plurality of input signals, wherein the input signals include: signals from other performance and debug monitoring circuits, signals from combinatorial logic circuits, and configuration values. The combinatorial stage may be configured to perform one or more logical operations on a selected sub-set of the input signals. The counter may be configured to increment based, at least in part, upon a result of the combinatorial stage.
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公开(公告)号：US20230052075A1
公开(公告)日：2023-02-16
申请号：US17495804
申请日：2021-10-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Gabriel T. DAGANI , Gregory BERGSCHNEIDER , David C. TANNENBAUM
Abstract: A system and a method are disclosed for varying a pixel-rate functionality of a GPU as an optional feature without an explicit implementation from within an application. User interface (UI) content may be detected in a draw call of an application and a variable-rate shader lookup map may be generated based on the detected UI content. A pixel rate of 3D content may be increased using the variable-rate shader lookup map. Additionally or alternatively, other conditions may be detected for increasing the pixel rate, such as using information in an application profile, detecting high or low luminance values, detecting motion and/or detecting temporal anti-aliasing.
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Patent Agency Ranking
公开(公告)号：US20220067876A1
公开(公告)日：2022-03-03
申请号：US17146491
申请日：2021-01-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sushant KONDGULI , Arun RADHAKRISHNAN , Zachary D. NEYLAND , David C. TANNENBAUM
Abstract: A method of processing a workload in a graphics processing unit (GPU) may include detecting a work item of the workload in the GPU, determining a cache policy for the work item, and operating at least a portion of a cache memory hierarchy in the GPU for at least a portion of the work item based on the cache policy. The work item may be detected based on information received from an application and/or monitoring one or more performance counters by a driver and/or hardware detection logic. The method may further include monitoring one or more performance counters, wherein the cache policy for the work item may be determined and/or changed based on the one or more performance counters. The cache policy for the work item may be selected based on a runtime learning model.
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公开(公告)号：US20220036634A1
公开(公告)日：2022-02-03
申请号：US17503259
申请日：2021-10-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Keshavan VARADARAJAN , Veynu NARASIMAN , David C. TANNENBAUM
IPC: G06T15/00
Abstract: A method of packing coverage in a graphics processing unit (GPU) may include receiving an indication for a portion of an image, determining, based on the indication, a packing technique for the portion of the image, and packing coverage for the portion of the image based on the packing technique. The indication may include one or more of: an importance, a quality, a level of interest, a level of detail, or a variable-rate shading (VRS) level. The indication may be received from an application. The packing technique may include array merging. The array merging may include quad merging. The packing technique may include pixel piling. The packing technique may be a first packing technique, and the method may further include determining, based on the indication, a second packing technique for the portion of the image, and packing coverage for the portion of the image based on the second packing technique.
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公开(公告)号：US20220066934A1
公开(公告)日：2022-03-03
申请号：US17086323
申请日：2020-10-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： David C. TANNENBAUM , Raun M. KRISCH , Christopher P. FRASCATI
IPC: G06F12/084
Abstract: A method for performing an atomic memory operation may include receiving an atomic input, receiving an address for an atomic memory location, and performing an atomic operation on the atomic memory location based on the atomic input, wherein performing the atomic operation may include performing a first operation on a first portion of the atomic input, and performing a second operation, which may be different from the first operation, on a second portion of the atomic input. The method may further include storing a result of the first operation in a first portion of the atomic memory location, and storing a result of the second operation in a second portion of the atomic memory location. The method may further include returning an original content of the first portion of the atomic memory location concatenated with an original content of the second portion of the atomic memory location.
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公开(公告)号：US20220036631A1
公开(公告)日：2022-02-03
申请号：US17168168
申请日：2021-02-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Keshavan VARADARAJAN , David C. TANNENBAUM , FNU GURUPAD
Abstract: A GPU includes shader cores and a shader warp packer unit. The shader warp packer unit may receive a first primitive associated with a first partially covered quad, and a second primitive associated with a second partially covered quad. The shader warp packer unit may determine that the first partially covered quad and the second partially covered quad have non-overlapping coverage. The shader warp packer unit may pack the first partially covered quad and the second partially covered quad into a packed quad. The shader warp packer unit may send the packed quad to the shader cores. The first partially covered quad and the second partially covered quad may be spatially disjoint from each other. The shader cores may receive and process the packed quad with no loss of information relative to the shader cores individually processing the first partially covered quad and the second partially covered quad.
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10.发明申请公开(公告)号：US20200184715A1
公开(公告)日：2020-06-11
申请号：US16438446
申请日：2019-06-11
Applicant: Samsung Electronics Co., Ltd.
Abstract: A computer-implemented redundant-coverage discard method and apparatus for reducing pixel shader work in a tile-based graphics rendering pipeline is disclosed. A coverage block information (CBI) FIFO buffer is disposed within an early coverage discard (ECD) logic section. The FIFO buffer receives and buffers coverage blocks in FIFO order. At least one coverage block that matches the block position within the TCPM is updated. The TCPM stores per-pixel primitive coverage information. The FIFO buffer buffers a moving window of the coverage blocks. Incoming primitive information associated with the coverage blocks is compared with the per-pixel primitive coverage information stored in the tile coverage-primitive map (TCPM) table at the corresponding positions for the live coverages only. Any preceding overlapping coverage within the moving window of the coverage blocks is rejected. An alternate embodiment uses a doubly linked-list rather than a FIFO buffer.
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