公开(公告)号：US20200066978A1

公开(公告)日：2020-02-27

申请号：US16423557

申请日：2019-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pyojin JEON ,  Jaeho JUNG ,  Gwang-Hyun BAEK

IPC: H01L45/00

Abstract: A variable resistance memory device includes an interlayer insulating structure on a substrate, the interlayer insulating structure having a hole, a bottom electrode in a lower portion of the hole, and a pattern in an upper portion of the hole, the pattern including at least one of a phase change pattern or an intermediate electrode, a sidewall of the pattern defining an angle with a top surface of the substrate, and the angle decreasing as a vertical distance from the substrate increases.

公开(公告)号：US20250079359A1

公开(公告)日：2025-03-06

申请号：US18785080

申请日：2024-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong Wan HAN ,  Byung Kyu KIM ,  Jeonghun KIM ,  Tae-Hong KIM ,  Pyojin JEON ,  Seok Hwan JEONG

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532 ,  H10B12/00

Abstract: A semiconductor chip includes a substrate. a device layer and an interconnection layer sequentially on the substrate, and a bonding pad on the interconnection layer. A bottom surface of the bonding pad may be located at a constant level, and a side surface of the bonding pad may have a roughened shape.