公开(公告)号：US20250140676A1

公开(公告)日：2025-05-01

申请号：US18637844

申请日：2024-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongrim SEO ,  Pyunghwa HAN ,  JoongSun KIM

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A wiring structure may include a first wiring layer including a first via pad, a first insulating layer covering the first wiring layer, a second wiring layer on the first insulating layer and including a second via pad defining a hole, a second insulating layer on the first insulating layer and covering the second wiring layer, a third wiring layer on the second insulating layer and including a third via pad, and a via integrally penetrating the first insulating layer and the second insulating layer, filling the hole of the second via pad, and connecting the first via pad, the second via pad, and the third via pad to each other, wherein the first insulating layer covers upper and side surfaces of the first via pad, and a diameter of the first via pad is smaller than diameters of the second via pad and the third via pad.

公开(公告)号：US20250140619A1

公开(公告)日：2025-05-01

申请号：US18927331

申请日：2024-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongsoo KIM ,  Chobi KIM ,  Pyunghwa HAN

IPC: H01L23/14 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes: a first interconnection structure; an expanded layer arranged on the first interconnection structure, the expanded layer comprising a plurality of expanded base layers; a semiconductor chip arranged in a mounting space and electrically connected to the first interconnection structure; a filling insulating layer configured to fill the mounting space; and a second interconnection structure arranged on the expanded layer and the filling insulating layer, the second interconnection structure electrically connected to the first interconnection structure through a plurality of via structures, in which a surface of a lowermost expanded base layer among the plurality of expanded base layers is positioned at a higher vertical level than a surface of the filling insulating layer, and a sink space is confined by the expanded layer and the filling insulating layer under a surface of the lowermost expanded base layer among the plurality of expanded base layers.