公开(公告)号：US20240206182A1

公开(公告)日：2024-06-20

申请号：US18523033

申请日：2023-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changmin CHOI ,  Ryoongbin LEE ,  Dongjin LEE ,  Junhee LIM

IPC: H10B43/40 ,  H10B41/10 ,  H10B41/40 ,  H10B43/10

CPC classification number: H10B43/40 ,  H10B41/10 ,  H10B41/40 ,  H10B43/10

Abstract: A non-volatile memory device including a memory cell array including a plurality of word lines stacked on a substrate in a first direction perpendicular to an upper surface of the substrate, and a common source line below the plurality of word lines, a plurality, of driving signal lines connected to a row decoder, and a plurality of pass transistor arrays each including a plurality of vertical pass transistors respectively connected the plurality of driving signal lines and the plurality of word lines, wherein each of the plurality of pass transistor arrays further include an active region including a drain to which at least two of the plurality of vertical pass transistors are simultaneously bonded, and a main contact applying a signal to the active region.