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公开(公告)号：US20240365550A1
公开(公告)日：2024-10-31
申请号：US18769334
申请日：2024-07-10
IPC分类号： H10B43/27 , H01L23/528 , H10B41/10 , H10B41/27 , H10B43/10
CPC分类号： H10B43/27 , H01L23/5283 , H10B41/10 , H10B41/27 , H10B43/10
摘要： A memory device includes a multi-layer stack disposed on a substrate and including conductive layers and dielectric layers stacked alternately, a channel layer penetrating through the multi-layer stack, a charge storage layer disposed between the conductive layers and the channel layer, a first conductive pillar and a second conductive pillar adjacent to the channel layer, a first interconnect structure connected to an end of the first conductive pillar, and a second interconnect structure connected to an end of the second conductive pillar. The end of the first conductive pillar connected to the first interconnect structure and the end of the second conductive pillar connected to the second interconnect structure are located on opposite sides of the multi-layer stack.
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公开(公告)号：US20240365548A1
公开(公告)日：2024-10-31
申请号：US18764371
申请日：2024-07-05
申请人： SK hynix Inc.
发明人： Ki Hong LEE , Ji Yeon BAEK , Seung Ho PYI
IPC分类号： H10B43/27 , H01L21/768 , H10B43/10 , H10B43/35
CPC分类号： H10B43/27 , H01L21/76898 , H10B43/10 , H10B43/35
摘要： A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.
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公开(公告)号：US12133386B2
公开(公告)日：2024-10-29
申请号：US17249247
申请日：2021-02-24
发明人： Yongqing Wang , Siping Hu
CPC分类号： H10B43/27 , H01L24/03 , H01L24/08 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/35
摘要： Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method for a 3D NAND memory device includes providing a substrate, forming at least one contact pad over a first portion of a face side of the substrate, forming memory cells over a second portion of the face side of the substrate, depositing a first dielectric layer to cover the at least one contact pad and the memory cells of, forming a first connecting pads over the first dielectric layer and connected to the at least one contact pad and the memory cells, bonding the first connecting pads with second connecting pads of a peripheral structure, and exposing the at least one contact pad from a back side of the substrate.
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4.发明授权公开(公告)号：US12133385B2
公开(公告)日：2024-10-29
申请号：US17117619
申请日：2020-12-10
发明人： Jason Guo , Qiang Tang
摘要： A three-dimensional (3D) memory device and a fabricating method for forming the same are disclosed. The 3D memory device can include an alternating conductor/dielectric layer stack disposed on a substrate, a first staircase structure and a second staircase structure formed in the alternating conductor/dielectric layer stack, a staircase bridge extending in a first direction and electrically connecting the first staircase structure and the second staircase structure, and a first bottom select gate segment covered or partially covered by the staircase bridge. The first bottom select gate segment can include an extended portion extending in a second direction different from the first direction.
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公开(公告)号：US20240355392A1
公开(公告)日：2024-10-24
申请号：US18640902
申请日：2024-04-19
发明人： Avinash Rajagiri , Pitamber Shukla
CPC分类号： G11C16/0483 , G11C16/10 , H10B43/10 , H10B43/27 , H10B43/35
摘要： Methods, systems, and devices for memory pillar selection transistor evaluation are described. A memory system may be configured to monitor threshold voltage characteristics of pillar selection transistors, which may include evaluations relative to certain subsets of the pillar selection transistors. For example, an activation voltage may be applied to the pillar selection transistors to determine whether threshold voltages associated with each subset of pillar selection transistors have shifted. Determining whether the threshold voltages have shifted may include determining whether an access parameter has been satisfied, such as a duration to program memory cells. For example, a relatively long duration may indicate that channels associated with pillar selection transistors have become less conductive for a given activation voltage.
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公开(公告)号：US20240339402A1
公开(公告)日：2024-10-10
申请号：US18382251
申请日：2023-10-20
发明人： Zhong ZHANG , Kun ZHANG , Wenxi ZHOU , Zhiliang XIA
IPC分类号： H01L23/528 , H01L21/768 , H01L23/522 , H10B41/10 , H10B41/27 , H10B43/10 , H10B43/27
CPC分类号： H01L23/5283 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H10B41/10 , H10B41/27 , H10B43/10 , H10B43/27
摘要： A memory device includes a stack structure and a first beam structure. The memory device includes array regions and an intermediate region arranged between the array regions in a first lateral direction. The stack structure includes a first block and a second block arranged in a second lateral direction. Each of the first block and the second block includes a wall-structure region. In the intermediate region, the wall-structure regions of the first block and the second block are separated by a staircase structure. The first beam structure is located in the intermediate region and extends along the second lateral direction. The first beam structure is connected to the wall-structure regions of the first block and the second block. The first beam structure includes first dielectric layers and electrode layers that are alternately stacked.
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公开(公告)号：US20240334703A1
公开(公告)日：2024-10-03
申请号：US18738970
申请日：2024-06-10
发明人： Anilkumar Chandolu , Indra V. Chary
摘要： Microelectronic devices include a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. Conductive contact structures extend through the stack structure. An insulative material is between the conductive contact structures and the tiers of the stack structure. In a lower tier portion of the stack structure, a conductive structure, of the conductive structures, has a portion extending a first width between a pair of the conductive contact structures. In a portion of the stack structure above the lower tier portion, an additional conductive structure, of the conductive structures, has an additional portion extending a second width between the pair of the conductive contact structures. The second width is greater than the first width. Related methods and electronic systems are also disclosed.
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8.发明公开公开(公告)号：US20240332180A1
公开(公告)日：2024-10-03
申请号：US18624522
申请日：2024-04-02
发明人： Teruo OKINA , Kengo KAJIWARA
IPC分类号： H01L23/528 , G11C16/04 , H01L23/522 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
CPC分类号： H01L23/5283 , G11C16/0483 , H01L23/5226 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
摘要： A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a source layer; a memory opening vertically extending through the alternating stack; and a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel laterally surrounded by the memory film and in contact with the source layer, a dielectric metal oxide liner laterally surrounded by the vertical semiconductor channel, and a dielectric core laterally surrounded by the dielectric metal oxide liner.
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公开(公告)号：US20240331738A1
公开(公告)日：2024-10-03
申请号：US18348959
申请日：2023-07-07
申请人： SK hynix Inc.
发明人： Nam Jae LEE
摘要： A semiconductor device including a first block word line, and a first channel layer located in the first block word line. the semiconductor device including a source pad connected to the first channel layer and located on the first block word line, and a first drain pad connected to the first channel layer and located on the first block word line. The semiconductor device including a global word line connected to the source pad, and a first local word line connected to the first drain pad.
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公开(公告)号：US12108599B2
公开(公告)日：2024-10-01
申请号：US18206402
申请日：2023-06-06
发明人： Geun-won Lim
摘要： A semiconductor memory device including: a common source line; a substrate on the common source line; a plurality of gate electrodes arranged on the substrate and spaced apart from each other in a first direction perpendicular to a top surface of the common source line; a plurality of insulation films arranged among the plurality of gate electrodes; a plurality of channel structures penetrating through the plurality of gate electrodes and the plurality of insulation films in the first direction; and a plurality of residual sacrificial films arranged on the substrate and spaced apart from each other in the first direction, wherein the plurality of gate electrodes are disposed on opposite sides of the plurality of residual sacrificial films.
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