公开(公告)号：US20220020691A1

公开(公告)日：2022-01-20

申请号：US17180491

申请日：2021-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYEONGYU YOU ,  JISU YU ,  JAE-WOO SEO ,  SEUNG MAN LIM

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/285 ,  H01L21/8238

Abstract: Disclosed is a semiconductor device comprising a first logic cell and a second logic cell on a substrate. Each of the first and second logic cells includes a first active region and a second active region that are adjacent to each other in a first direction, a gate electrode that runs across the first and second active regions and extends lengthwise in the first direction, and a first metal layer on the gate electrode. The first metal layer includes a first power line and a second power line that extend lengthwise in a second direction perpendicular to the first direction, and are parallel to each other. The first and second logic cells are adjacent to each other in the second direction along the first and second power lines. The first and second active regions extend lengthwise in the second direction from the first logic cell to the second logic cell.

公开(公告)号：US20210165947A1

公开(公告)日：2021-06-03

申请号：US17087915

申请日：2020-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAE-HO PARK ,  SANGHOON BAEK ,  JI SU YU ,  HYEON GYU YOU ,  SEUNG YOUNG LEE ,  SEUNG MAN LIM ,  MIN JAE JEONG ,  JONG HOON JUNG

IPC: G06F30/392 ,  H01L27/02 ,  G06F30/394

Abstract: A layout method is provided. The layout method may include placing first and second standard cells from a standard cell library, interconnecting the placed standard cells to generate a layout draft, confirming placement and routing at a boundary region between the interconnected standard cells, and revising the layout draft based on the confirmation. Each of the standard cells includes, in part, a conductive line that extends in the first direction and is interconnected to an adjacent standard cell through a source/drain via. To confirm the placement and routing, a first spaced distance from a tip of one of the conductive lines to a tip of the other conductive line, and a second spaced distance from the tip of the first conductive line to the cell boundary are compared with preset threshold values. Revising the layout draft may include adjusting a tip position of one of the conductive lines.