公开(公告)号：US20150235018A1

公开(公告)日：2015-08-20

申请号：US14624663

申请日：2015-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sandeep GUPTA ,  Gaurav KAKKAR

IPC: G06F21/36

CPC classification number: G06F21/36

Abstract: An electronic device, a method of an electronic device authenticating a user and a computer readable recording medium are provided, The electronic device includes a storage configured to store an identifier and attributes of a first object as authentication information, a display configured to display a plurality of authentication objects comprising a second object that has one or more of the attributes of the first object and has a form different from a form of the first object, in response to a request to perform an authentication procedure, and a controller configured to authenticate a user based on an attribute of an authentication object selected by the user from among the plurality of displayed authentication objects and the stored authentication information.

Abstract translation: 提供一种电子设备，用于认证用户的电子设备的方法和计算机可读记录介质。电子设备包括：存储器，被配置为存储第一对象的标识符和属性作为认证信息;显示器，被配置为显示多个 响应于执行认证过程的请求，包括具有第一对象的一个​​或多个属性并且具有与第一对象的形式不同的形式的第二对象的认证对象，以及控制器，被配置为认证 基于用户从多个显示的认证对象中选择的认证对象的属性和所存储的认证信息。

公开(公告)号：US20190102197A1

公开(公告)日：2019-04-04

申请号：US15853628

申请日：2017-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aditya KUMAR ,  Sandeep GUPTA ,  Bonnie Collett SEXTON

IPC: G06F9/30 ,  G06F9/38

Abstract: According to one general aspect, an apparatus may include a decoder circuit, a scheduler circuit, and an execution circuit. The decoder circuit may be configured to detect, within an instruction stream, a first instruction followed by a second instruction, wherein the first instruction takes as input a dividend and a divisor, and wherein the second instruction produces a remainder. The scheduler circuit may be configured to: merge the first and second instructions into a third instruction, wherein the third instruction takes as input the dividend and the divisor, and produces the remainder, replace, within an instruction pipeline, the first instruction with the third instruction, and delete, within the instruction pipeline, the second instruction. The execution circuit may be configured to execute the third instruction.