SYSTEM AND METHOD FOR MERGING DIVIDE AND MULTIPLY-SUBTRACT OPERATIONS

    公开(公告)号:US20190102197A1

    公开(公告)日:2019-04-04

    申请号:US15853628

    申请日:2017-12-22

    Abstract: According to one general aspect, an apparatus may include a decoder circuit, a scheduler circuit, and an execution circuit. The decoder circuit may be configured to detect, within an instruction stream, a first instruction followed by a second instruction, wherein the first instruction takes as input a dividend and a divisor, and wherein the second instruction produces a remainder. The scheduler circuit may be configured to: merge the first and second instructions into a third instruction, wherein the third instruction takes as input the dividend and the divisor, and produces the remainder, replace, within an instruction pipeline, the first instruction with the third instruction, and delete, within the instruction pipeline, the second instruction. The execution circuit may be configured to execute the third instruction.

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