公开(公告)号：US09424954B2

公开(公告)日：2016-08-23

申请号：US14150092

申请日：2014-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taek-Sung Kim ,  Sangbo Lee ,  SoonYong Hur

IPC: G11C7/00 ,  G11C29/00

CPC classification number: G11C29/886 ,  G11C29/006 ,  G11C2229/746 ,  H01L2224/16145

Abstract: A semiconductor package includes first and second slave chips stacked vertically; and a master chip connected to the first and second slave chips, each of the slave chips including, a plurality of memory blocks, and a redundancy block, and the master chip including, a fuse block configured to repair a defective memory block detected from the first slave chip and a defective memory block detected from the second slave chip by using the redundancy block of the first slave chip and the redundancy block of the second slave chip, respectively, and a block selection circuit configured to, connect the redundancy blocks of the first and second slave chips, one or more non-defective ones of the plurality of memory blocks of the first slave chip, and one or more non-defective ones of the plurality of memory blocks of the second slave chip to an input/output circuit.

Abstract translation: 半导体封装包括垂直堆叠的第一和第二从芯片; 以及连接到第一和第二从芯片的主芯片，每个从芯片包括多个存储器块和冗余块，并且所述主芯片包括：熔丝块，被配置为修复从所述第一和第二从芯片检测到的缺陷存储器块 分别通过使用第一从芯片的冗余块和第二从芯片的冗余块从第二从芯片检测到的第一从芯片和缺陷存储块，以及块选择电路，被配置为将 第一和第二从属芯片，第一从芯片的多个存储块中的一个或多个非缺陷存储器块，以及第二从芯片的多个存储块中的一个或多个非缺陷存储器块输入到/输出电路 。