公开(公告)号：US12191288B2

公开(公告)日：2025-01-07

申请号：US17947113

申请日：2022-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangnam Jeong ,  Yunhee Lee

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: Provided are an integrated voltage regulator (IVR) package with a minimized size including one or more inductors and one or more capacitors together with an IVR chip and improving characteristics of a voltage regulator (VR), and an IVR system package including the IVR package. The IVR package includes a package substrate, a stacked structure mounted on the package substrate and having a stack structure in which a passive device chip including one or more capacitors and an IVR chip including a voltage regulator are stacked, and an intermediate substrate disposed on the package substrate in a structure surrounding the stacked structure, the intermediate substrate including vias therein. The one or more inductors are included in the stacked structure or the intermediate substrate.

公开(公告)号：US10797030B2

公开(公告)日：2020-10-06

申请号：US15867686

申请日：2018-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangnam Jeong ,  IlJoon Kim ,  SunWon Kang

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/522 ,  H01L23/48 ,  H01L23/538 ,  H01L23/50 ,  H01L23/498

Abstract: Disclosed is a semiconductor package including a semiconductor chip, a first outer capacitor on the semiconductor chip including a first electrode and a second electrode, a second outer capacitor on the semiconductor chip including a first electrode pattern and a second electrode pattern, and a conductive pattern on the semiconductor chip and electrically connected to the first electrode of the first outer capacitor and the first electrode pattern of the second outer capacitor. The second electrode of the first outer capacitor is insulated from the second electrode pattern of the second outer capacitor.

公开(公告)号：US20230127676A1

公开(公告)日：2023-04-27

申请号：US17858441

申请日：2022-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook Park ,  Sangnam Jeong

IPC: H01L23/66 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package includes a wiring board including at least one pair of connection structures electrically connecting at least one pair of differential signal transmission lines and at least one pair of differential signal transmission terminals, respectively. The at least one pair of connection structures includes first via structures staggered in a vertical direction, at least one first connection line electrically connecting the first via structures, second via structures staggered in the vertical direction, and at least one second connection line electrically connecting the second via structures. The at least one first connection line is spaced apart from the at least one second connection line in the vertical direction and electrically insulated therefrom, and intersects the at least one second connection line in the vertical direction.

公开(公告)号：US11018121B2

公开(公告)日：2021-05-25

申请号：US16438430

申请日：2019-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangnam Jeong ,  IlJoon Kim ,  SunWon Kang

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/522 ,  H01L23/48 ,  H01L23/538 ,  H01L23/50 ,  H01L23/498

Abstract: Disclosed is a semiconductor package including a semiconductor chip, a first outer capacitor on the semiconductor chip including a first electrode and a second electrode, a second outer capacitor on the semiconductor chip including a first electrode pattern and a second electrode pattern, and a conductive pattern on the semiconductor chip and electrically connected to the first electrode of the first outer capacitor and the first electrode pattern of the second outer capacitor. The second electrode of the first outer capacitor is insulated from the second electrode pattern of the second outer capacitor.