公开(公告)号：US20130320457A1

公开(公告)日：2013-12-05

申请号：US13909404

申请日：2013-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Chan Lim ,  Sang-Pil Sim ,  Dong-Kyun Sohn ,  Su-Youn Yi

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device including source drain stressors is provided. The semiconductor device includes a gate structure including a gate insulating layer and a gate electrode on a semiconductor substrate. Gate spacers may be disposed on sidewalls of the gate structure and a stressor pattern including an impurity region is disposed on a side of the gate structure. The stressor pattern includes a protruded portion having a top surface higher than a bottom surface of the gate structure and a facet in the protruded portion. The facet is slanted at a predetermined angle with respect to an upper surface of the semiconductor substrate and forms a concave portion with one of the gate spacers. A blocking insulating layer may extend conformally on the stressor pattern and the gate spacers and an insulating wing pattern is disposed in the concave portion on the blocking insulating layer.

公开(公告)号：US09502413B2

公开(公告)日：2016-11-22

申请号：US14828108

申请日：2015-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Chan Lim ,  Sang-Pil Sim ,  Dong-Kyun Sohn ,  Su-Youn Yi

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device including source drain stressors is provided. The semiconductor device includes a gate structure including a gate insulating layer and a gate electrode on a semiconductor substrate. Gate spacers may be disposed on sidewalls of the gate structure and a stressor pattern including an impurity region is disposed on a side of the gate structure. The stressor pattern includes a protruded portion having a top surface higher than a bottom surface of the gate structure and a facet in the protruded portion. The facet is slanted at a predetermined angle with respect to an upper surface of the semiconductor substrate and forms a concave portion with one of the gate spacers. A blocking insulating layer may extend conformally on the stressor pattern and the gate spacers and an insulating wing pattern is disposed in the concave portion on the blocking insulating layer.

Abstract translation: 提供了包括源漏应力源的半导体器件。 半导体器件包括在半导体衬底上包括栅极绝缘层和栅电极的栅极结构。 栅极间隔物可以设置在栅极结构的侧壁上，并且包括杂质区的应力源图案设置在栅极结构的一侧。 应力源图案包括具有高于栅极结构的底表面的顶表面和突出部分中的刻面的突出部分。 小面相对于半导体衬底的上表面以预定角度倾斜，并与其中一个栅极间隔物形成凹部。 阻挡绝缘层可以在应力器图案上保形地延伸，并且栅极间隔件和绝缘翼图案设置在阻挡绝缘层上的凹部中。

公开(公告)号：US20150357329A1

公开(公告)日：2015-12-10

申请号：US14828108

申请日：2015-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Chan Lim ,  Sang-Pil Sim ,  Dong-Kyun Sohn ,  Su-Youn Yi

IPC: H01L27/092 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device including source drain stressors is provided. The semiconductor device includes a gate structure including a gate insulating layer and a gate electrode on a semiconductor substrate. Gate spacers may be disposed on sidewalls of the gate structure and a stressor pattern including an impurity region is disposed on a side of the gate structure. The stressor pattern includes a protruded portion having a top surface higher than a bottom surface of the gate structure and a facet in the protruded portion. The facet is slanted at a predetermined angle with respect to an upper surface of the semiconductor substrate and forms a concave portion with one of the gate spacers. A blocking insulating layer may extend conformally on the stressor pattern and the gate spacers and an insulating wing pattern is disposed in the concave portion on the blocking insulating layer.

Abstract translation: 提供了包括源漏应力源的半导体器件。 半导体器件包括在半导体衬底上包括栅极绝缘层和栅电极的栅极结构。 栅极间隔物可以设置在栅极结构的侧壁上，并且包括杂质区的应力源图案设置在栅极结构的一侧。 应力源图案包括具有高于栅极结构的底表面的顶表面和突出部分中的刻面的突出部分。 小面相对于半导体衬底的上表面以预定角度倾斜，并与其中一个栅极间隔物形成凹部。 阻挡绝缘层可以在应力器图案上保形地延伸，并且栅极间隔件和绝缘翼图案设置在阻挡绝缘层上的凹部中。