公开(公告)号：US09502413B2

公开(公告)日：2016-11-22

申请号：US14828108

申请日：2015-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Chan Lim ,  Sang-Pil Sim ,  Dong-Kyun Sohn ,  Su-Youn Yi

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device including source drain stressors is provided. The semiconductor device includes a gate structure including a gate insulating layer and a gate electrode on a semiconductor substrate. Gate spacers may be disposed on sidewalls of the gate structure and a stressor pattern including an impurity region is disposed on a side of the gate structure. The stressor pattern includes a protruded portion having a top surface higher than a bottom surface of the gate structure and a facet in the protruded portion. The facet is slanted at a predetermined angle with respect to an upper surface of the semiconductor substrate and forms a concave portion with one of the gate spacers. A blocking insulating layer may extend conformally on the stressor pattern and the gate spacers and an insulating wing pattern is disposed in the concave portion on the blocking insulating layer.

Abstract translation: 提供了包括源漏应力源的半导体器件。 半导体器件包括在半导体衬底上包括栅极绝缘层和栅电极的栅极结构。 栅极间隔物可以设置在栅极结构的侧壁上，并且包括杂质区的应力源图案设置在栅极结构的一侧。 应力源图案包括具有高于栅极结构的底表面的顶表面和突出部分中的刻面的突出部分。 小面相对于半导体衬底的上表面以预定角度倾斜，并与其中一个栅极间隔物形成凹部。 阻挡绝缘层可以在应力器图案上保形地延伸，并且栅极间隔件和绝缘翼图案设置在阻挡绝缘层上的凹部中。

公开(公告)号：US20150357329A1

公开(公告)日：2015-12-10

申请号：US14828108

申请日：2015-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Chan Lim ,  Sang-Pil Sim ,  Dong-Kyun Sohn ,  Su-Youn Yi

IPC: H01L27/092 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device including source drain stressors is provided. The semiconductor device includes a gate structure including a gate insulating layer and a gate electrode on a semiconductor substrate. Gate spacers may be disposed on sidewalls of the gate structure and a stressor pattern including an impurity region is disposed on a side of the gate structure. The stressor pattern includes a protruded portion having a top surface higher than a bottom surface of the gate structure and a facet in the protruded portion. The facet is slanted at a predetermined angle with respect to an upper surface of the semiconductor substrate and forms a concave portion with one of the gate spacers. A blocking insulating layer may extend conformally on the stressor pattern and the gate spacers and an insulating wing pattern is disposed in the concave portion on the blocking insulating layer.

Abstract translation: 提供了包括源漏应力源的半导体器件。 半导体器件包括在半导体衬底上包括栅极绝缘层和栅电极的栅极结构。 栅极间隔物可以设置在栅极结构的侧壁上，并且包括杂质区的应力源图案设置在栅极结构的一侧。 应力源图案包括具有高于栅极结构的底表面的顶表面和突出部分中的刻面的突出部分。 小面相对于半导体衬底的上表面以预定角度倾斜，并与其中一个栅极间隔物形成凹部。 阻挡绝缘层可以在应力器图案上保形地延伸，并且栅极间隔件和绝缘翼图案设置在阻挡绝缘层上的凹部中。

公开(公告)号：US09141751B2

公开(公告)日：2015-09-22

申请号：US13950799

申请日：2013-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jong Lee ,  Soo-Han Choi ,  Jung-Ho Do ,  Chul-Hong Park ,  Sang-Pil Sim

IPC: G06F17/50 ,  H01L21/308

CPC classification number: G06F17/5081 ,  H01L21/3086

Abstract: A method of forming a pattern includes defining a plurality of patterns, defining a plurality of pitch violating patterns that contact the plurality of patterns and correspond to regions between the patterns, classifying the plurality of pitch violating patterns into a first region and a second region that is adjacent to the first region, selecting one of the first region and the second region, and forming an initial pattern defined as the selected first or second region. The selecting includes performing at least one of i) selecting a region that contact dummy patterns, ii) selecting a region of a same kind as one region, and iii) selecting a region that contacts a concave part of an enclosure from the first region and the second region.

Abstract translation: 形成图案的方法包括限定多个图案，限定接触所述多个图案并对应于所述图案之间的区域的多个倾斜违规图案，将所述多个音高违规图案分类为第一区域和第二区域， 与第一区域相邻，选择第一区域和第二区域中的一个，以及形成被定义为所选择的第一或第二区域的初始图案。 所述选择包括执行以下各项中的至少一个：i）选择接触虚拟图案的区域，ii）选择与一个区域相同类型的区域，以及iii）从所述第一区域选择与外壳的凹部接触的区域，以及 第二个地区。

公开(公告)号：US20240213317A1

公开(公告)日：2024-06-27

申请号：US18596461

申请日：2024-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu MAEDA ,  Hee-Soo Kang ,  Sang-Pil Sim ,  Soo-Hun Hong

IPC: H01L29/06 ,  B82Y10/00 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/0692 ,  B82Y10/00 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/775

Abstract: A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.

公开(公告)号：US20130320457A1

公开(公告)日：2013-12-05

申请号：US13909404

申请日：2013-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Chan Lim ,  Sang-Pil Sim ,  Dong-Kyun Sohn ,  Su-Youn Yi

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device including source drain stressors is provided. The semiconductor device includes a gate structure including a gate insulating layer and a gate electrode on a semiconductor substrate. Gate spacers may be disposed on sidewalls of the gate structure and a stressor pattern including an impurity region is disposed on a side of the gate structure. The stressor pattern includes a protruded portion having a top surface higher than a bottom surface of the gate structure and a facet in the protruded portion. The facet is slanted at a predetermined angle with respect to an upper surface of the semiconductor substrate and forms a concave portion with one of the gate spacers. A blocking insulating layer may extend conformally on the stressor pattern and the gate spacers and an insulating wing pattern is disposed in the concave portion on the blocking insulating layer.

公开(公告)号：US20210066454A1

公开(公告)日：2021-03-04

申请号：US17098412

申请日：2020-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Hee-Soo Kang ,  Sang-Pil Sim ,  Soo-Hun Hong

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  B82Y10/00 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L27/088 ,  H01L29/10 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/49 ,  H01L29/51

Abstract: A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.

公开(公告)号：US10002943B2

公开(公告)日：2018-06-19

申请号：US15164246

申请日：2016-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo-Hun Hong ,  Hee-Soo Kang ,  Hyun-Jo Kim ,  Sang-Pil Sim ,  Hee-Don Jung

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/165

CPC classification number: H01L29/66545 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a substrate including first to third fins aligned in a first direction, a first trench arranged between the first fin and the second fin, and a second trench arranged between the second fin and the third fin. The semiconductor device further includes a first field insulating film arranged in the first trench, a second field insulating film formed in the second trench, a first dummy gate arranged on the first field insulating film and a second dummy gate at least partly arranged on the second field insulating film. A lower surface of the second field insulating film is arranged to be lower than a lower surface of the first field insulating film.

公开(公告)号：US20140162460A1

公开(公告)日：2014-06-12

申请号：US13950799

申请日：2013-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUN-JONG LEE ,  Soo-Han Choi ,  Jung-Ho Do ,  Chul-Hong Park ,  Sang-Pil Sim

IPC: G06F17/50 ,  H01L21/308

CPC classification number: G06F17/5081 ,  H01L21/3086

Abstract: A method of forming a pattern includes defining a plurality of patterns, defining a plurality of pitch violating patterns that contact the plurality of patterns and correspond to regions between the patterns, classifying the plurality of pitch violating patterns into a first region and a second region that is adjacent to the first region, selecting one of the first region and the second region, and forming an initial pattern defined as the selected first or second region. The selecting includes performing at least one of i) selecting a region that contact dummy patterns, ii) selecting a region of a same kind as one region, and iii) selecting a region that contacts a concave part of an enclosure from the first region and the second region.

Abstract translation: 形成图案的方法包括限定多个图案，限定接触所述多个图案并对应于所述图案之间的区域的多个倾斜违规图案，将所述多个音高违规图案分类为第一区域和第二区域， 与第一区域相邻，选择第一区域和第二区域中的一个，以及形成被定义为所选择的第一或第二区域的初始图案。 所述选择包括执行以下各项中的至少一个：i）选择接触虚拟图案的区域，ii）选择与一个区域相同类型的区域，以及iii）从所述第一区域选择与外壳的凹部接触的区域，以及 第二个地区。

公开(公告)号：US10269928B2

公开(公告)日：2019-04-23

申请号：US15717843

申请日：2017-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo-Hun Hong ,  Hee-Soo Kang ,  Hyun-Jo Kim ,  Sang-Pil Sim ,  Hee-Don Jung

IPC: H01L29/161 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L21/762 ,  H01L29/78 ,  H01L29/165

Abstract: A semiconductor device includes a substrate including first to third fins aligned in a first direction, a first trench arranged between the first fin and the second fin, and a second trench arranged between the second fin and the third fin. The semiconductor device further includes a first field insulating film arranged in the first trench, a second field insulating film formed in the second trench, a first dummy gate arranged on the first field insulating film and a second dummy gate at least partly arranged on the second field insulating film. A lower surface of the second field insulating film is arranged to be lower than a lower surface of the first field insulating film.

公开(公告)号：US08878309B1

公开(公告)日：2014-11-04

申请号：US14102897

申请日：2013-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo-Hun Hong ,  Hee-Soo Kang ,  Hyun-Jo Kim ,  Sang-Pil Sim ,  Hee-Don Jung

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823481

Abstract: A semiconductor device includes a substrate having first, second and third fins longitudinally aligned in a first direction. A first trench extends between the first and second fins, and a second trench extends between the second and third fins. A first portion of field insulating material is disposed in the first trench, and a second portion of field insulating material is disposed in the second trench. An upper surface of the second portion of the field insulating material is recessed in the second trench at a level below uppermost surfaces of the second and third fins. A first dummy gate is disposed on an upper surface of the first portion of the field insulating material, and a second dummy gate at least partially extends into the second trench to the upper surface of the second portion of the field insulating material.

Abstract translation: 半导体器件包括具有沿第一方向纵向排列的第一，第二和第三鳍片的衬底。 第一沟槽在第一和第二鳍之间延伸，第二沟槽在第二和第三鳍之间延伸。 场绝缘材料的第一部分设置在第一沟槽中，场绝缘材料的第二部分设置在第二沟槽中。 场绝缘材料的第二部分的上表面在第二沟槽中凹陷在第二和第三鳍片的最上表面以下的水平面处。 第一伪栅极设置在场绝缘材料的第一部分的上表面上，并且第二伪栅极至少部分地延伸到第二沟槽中至场绝缘材料的第二部分的上表面。