公开(公告)号：US20190158109A1

公开(公告)日：2019-05-23

申请号：US16191367

申请日：2018-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anil KAVALA ,  Seon-kyoo LEE ,  Byung-hoon JEONG ,  Jeong-don IHM ,  Young-don CHOI

IPC: H03M1/78 ,  G11C5/14 ,  G05F3/08

CPC classification number: H03M1/785 ,  G05F3/08 ,  G11C5/147 ,  G11C7/14

Abstract: A semiconductor device includes a reference voltage generator configured to output a reference voltage. The reference voltage generator includes a boosting code circuit and a first digital-analog converter (DAC). The boosting code circuit includes a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse. The first DAC is configured to output the reference voltage by converting the first boosting code. The first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.

公开(公告)号：US20170052225A1

公开(公告)日：2017-02-23

申请号：US15170940

申请日：2016-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-kyoo LEE ,  Jeong-don IHM ,  Byung-hoon JEONG ,  Dae-woon KANG ,  Tae-sung LEE ,  Sang-lok KIM

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/318392 ,  G01R31/31708

Abstract: A semiconductor chip, a test system, and a method of testing the semiconductor chip. The semiconductor chip includes a pulse generator configured to generate a test pulse in response to a test request; a logic chain comprising a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and a detector configured to detect a logic level of an output signal of each of the logic devices and output a detection result indicating a degree of an inter-symbol interference (ISI).

Abstract translation: 半导体芯片，测试系统和测试半导体芯片的方法。 半导体芯片包括：脉冲发生器，被配置为响应于测试请求产生测试脉冲; 逻辑链，包括彼此串联连接并顺次传送测试脉冲的多个逻辑器件; 以及检测器，被配置为检测每个逻辑器件的输出信号的逻辑电平，并输出指示符号间干扰程度（ISI）的检测结果。