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公开(公告)号:US20210311703A1
公开(公告)日:2021-10-07
申请号:US17212474
申请日:2021-03-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyunpil Kim , Hyunwoo Sim , Seongwoo Ahn , Hasong Kim , Doyoung Lee
Abstract: A neural network device includes a calculation circuit that includes a first multiplier, a second multiplier, an align shifter, and an adder. The adder shares the first multiplier and the second multiplier. The calculation circuit performs a first dot product operation on a plurality of floating point data pairs or a second dot product operation on a plurality of integer data pairs. In the first dot product operation, the calculation circuit obtains a plurality of fraction multiplication results from the plurality of floating point data pairs, respectively, using the first multiplier, adds the plurality of fraction multiplication results using the adder and outputs first cumulative data. In the second dot product operation, the calculation circuit obtains a plurality of integer multiplication results from the plurality of integer data pairs, respectively, using the second multiplier, adds the plurality of integer multiplication results using the adder, and outputs second cumulative data.
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公开(公告)号:US12079591B2
公开(公告)日:2024-09-03
申请号:US17217398
申请日:2021-03-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyunpil Kim , Hyunwoo Sim , Seongwoo Ahn , Hasong Kim , Doyoung Lee
CPC classification number: G06F7/4876 , G06F5/01 , G06F7/22 , G06F7/49921 , G06F7/5443 , G06F17/16 , G06N3/02
Abstract: A neural network device includes a floating-point arithmetic circuit configured to perform a dot product operation and an accumulation operation; and a buffer configured to store first cumulative data generated by the floating-point arithmetic circuit, wherein the floating-point arithmetic circuit is further configured to perform the dot product operation and the accumulation operation by: identifying a maximum value from a plurality of exponent addition results, obtained by respectively adding exponents of a plurality of floating-point data pairs, and an exponent value of the first cumulative data; performing, based on the maximum value, an align shift of a plurality of fraction multiplication results, obtained by respectively multiplying fractions of the plurality of floating-point data pairs, and a fraction part of the first cumulative data; and performing a summation of the plurality of aligned fraction multiplication results and the aligned fraction part of the first cumulative data.
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公开(公告)号:US20210312012A1
公开(公告)日:2021-10-07
申请号:US17217398
申请日:2021-03-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyunpil Kim , Hyunwoo Sim , Seongwoo Ahn , Hasong Kim , Doyoung Lee
Abstract: A neural network device includes a floating-point arithmetic circuit configured to perform a dot product operation and an accumulation operation; and a buffer configured to store first cumulative data generated by the floating-point arithmetic circuit, wherein the floating-point arithmetic circuit is further configured to perform the dot product operation and the accumulation operation by: identifying a maximum value from a plurality of exponent addition results, obtained by respectively adding exponents of a plurality of floating-point data pairs, and an exponent value of the first cumulative data; performing, based on the maximum value, an align shift of a plurality of fraction multiplication results, obtained by respectively multiplying fractions of the plurality of floating-point data pairs, and a fraction part of the first cumulative data; and performing a summation of the plurality of aligned fraction multiplication results and the aligned fraction part of the first cumulative data.
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公开(公告)号:US11340876B2
公开(公告)日:2022-05-24
申请号:US16687284
申请日:2019-11-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Deok Hwan Kim , Seongwoo Ahn , Soobok Yeo , Keoncheol Shin
Abstract: A method which is implemented by a processor of an electronic device includes receiving a program code directing operations to be processed by heterogeneous processors, receiving libraries to be referenced by the heterogeneous processors for processing the operations, receiving library information associated with attributes of processing the operations based on the libraries, determining processors, which will process the operations, from heterogeneous processors with reference to the library information such that each processor of the heterogeneous processors processes one or more assigned operations of the operations, and compiling sub portions divided from a whole portion of the program code so as to respectively correspond to the determined processors in a state where the sub portions respectively correspond to some libraries to be referenced by the determined processors.
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公开(公告)号:US12223289B2
公开(公告)日:2025-02-11
申请号:US17212474
申请日:2021-03-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyunpil Kim , Hyunwoo Sim , Seongwoo Ahn , Hasong Kim , Doyoung Lee
Abstract: A neural network device includes a calculation circuit that includes a first multiplier, a second multiplier, an align shifter, and an adder. The adder shares the first multiplier and the second multiplier. The calculation circuit performs a first dot product operation on a plurality of floating point data pairs or a second dot product operation on a plurality of integer data pairs. In the first dot product operation, the calculation circuit obtains a plurality of fraction multiplication results from the plurality of floating point data pairs, respectively, using the first multiplier, adds the plurality of fraction multiplication results using the adder and outputs first cumulative data. In the second dot product operation, the calculation circuit obtains a plurality of integer multiplication results from the plurality of integer data pairs, respectively, using the second multiplier, adds the plurality of integer multiplication results using the adder, and outputs second cumulative data.
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公开(公告)号:US10061559B2
公开(公告)日:2018-08-28
申请号:US15134842
申请日:2016-04-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyunpil Kim , Seongwoo Ahn
CPC classification number: G06F7/4812 , G06F7/523 , G06F7/5324 , G06F7/57
Abstract: Methods and apparatuses for performing arithmetic operations efficiently and quickly are described. Such arithmetic operations include, but are not limited to, multiplying 2N bit integers, multiplying multiple N-bit integers simultaneously, multiplying 2N bit complex numbers, and other multiplication operations involving coefficients, complex numbers, and complex conjugate numbers.
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