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    NEURAL NETWORK DEVICE FOR NEURAL NETWORK OPERATION, OPERATING METHOD OF THE NEURAL NETWORK DEVICE, AND APPLICATION PROCESSOR INCLUDING THE SAME
    1.
    发明申请
    NEURAL NETWORK DEVICE FOR NEURAL NETWORK OPERATION, OPERATING METHOD OF THE NEURAL NETWORK DEVICE, AND APPLICATION PROCESSOR INCLUDING THE SAME 有权

    公开(公告)号：US20210311703A1

    公开(公告)日：2021-10-07

    申请号：US17212474

    申请日：2021-03-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunpil Kim ,  Hyunwoo Sim ,  Seongwoo Ahn ,  Hasong Kim ,  Doyoung Lee

    IPC: G06F7/487 ,  G06N3/02 ,  G06F7/499

    Abstract: A neural network device includes a calculation circuit that includes a first multiplier, a second multiplier, an align shifter, and an adder. The adder shares the first multiplier and the second multiplier. The calculation circuit performs a first dot product operation on a plurality of floating point data pairs or a second dot product operation on a plurality of integer data pairs. In the first dot product operation, the calculation circuit obtains a plurality of fraction multiplication results from the plurality of floating point data pairs, respectively, using the first multiplier, adds the plurality of fraction multiplication results using the adder and outputs first cumulative data. In the second dot product operation, the calculation circuit obtains a plurality of integer multiplication results from the plurality of integer data pairs, respectively, using the second multiplier, adds the plurality of integer multiplication results using the adder, and outputs second cumulative data.

    NEURAL NETWORK DEVICE, METHOD OF OPERATING THE NEURAL NETWORK DEVICE, AND APPLICATION PROCESSOR INCLUDING THE NEURAL NETWORK DEVICE
    2.
    发明申请
    NEURAL NETWORK DEVICE, METHOD OF OPERATING THE NEURAL NETWORK DEVICE, AND APPLICATION PROCESSOR INCLUDING THE NEURAL NETWORK DEVICE 有权

    公开(公告)号：US20210312012A1

    公开(公告)日：2021-10-07

    申请号：US17217398

    申请日：2021-03-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunpil Kim ,  Hyunwoo Sim ,  Seongwoo Ahn ,  Hasong Kim ,  Doyoung Lee

    IPC: G06F17/16 ,  G06F7/487 ,  G06F7/22

    Abstract: A neural network device includes a floating-point arithmetic circuit configured to perform a dot product operation and an accumulation operation; and a buffer configured to store first cumulative data generated by the floating-point arithmetic circuit, wherein the floating-point arithmetic circuit is further configured to perform the dot product operation and the accumulation operation by: identifying a maximum value from a plurality of exponent addition results, obtained by respectively adding exponents of a plurality of floating-point data pairs, and an exponent value of the first cumulative data; performing, based on the maximum value, an align shift of a plurality of fraction multiplication results, obtained by respectively multiplying fractions of the plurality of floating-point data pairs, and a fraction part of the first cumulative data; and performing a summation of the plurality of aligned fraction multiplication results and the aligned fraction part of the first cumulative data.

    Neural network device for neural network operation, operating method of the neural network device, and application processor including the same
    3.
    发明授权
    Neural network device for neural network operation, operating method of the neural network device, and application processor including the same 有权

    公开(公告)号：US12223289B2

    公开(公告)日：2025-02-11

    申请号：US17212474

    申请日：2021-03-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunpil Kim ,  Hyunwoo Sim ,  Seongwoo Ahn ,  Hasong Kim ,  Doyoung Lee

    IPC: G06F7/487 ,  G06F7/544

    Abstract: A neural network device includes a calculation circuit that includes a first multiplier, a second multiplier, an align shifter, and an adder. The adder shares the first multiplier and the second multiplier. The calculation circuit performs a first dot product operation on a plurality of floating point data pairs or a second dot product operation on a plurality of integer data pairs. In the first dot product operation, the calculation circuit obtains a plurality of fraction multiplication results from the plurality of floating point data pairs, respectively, using the first multiplier, adds the plurality of fraction multiplication results using the adder and outputs first cumulative data. In the second dot product operation, the calculation circuit obtains a plurality of integer multiplication results from the plurality of integer data pairs, respectively, using the second multiplier, adds the plurality of integer multiplication results using the adder, and outputs second cumulative data.

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