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公开(公告)号:US10678420B2
公开(公告)日:2020-06-09
申请号:US15763330
申请日:2016-09-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yu-ri Choi , Hee-sung Park , Se-rin Ko , Dong-seok Kim , Jeong-pyo Lee , Seung-hyun Cho
IPC: G06F17/00 , G06F3/048 , G06F3/0486 , G06F3/0484 , G06F3/0488 , H04M1/725 , G05B19/409 , H04L12/28
Abstract: Disclosed is an electronic device. The present electronic device comprises a display, and a processor configured to display, through the display, a UI based on use patterns of a plurality of devices connected to a same network, wherein the UI comprises a device axis and a time axis, and provides information related to use of at least one device in a region where the device axis and the time axis intersect each other.
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2.
公开(公告)号:US10741242B2
公开(公告)日:2020-08-11
申请号:US16517724
申请日:2019-07-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Young-hun Seo , Seung-hyun Cho , Chang-ho Shin , Yong-jae Lee
IPC: G11C7/00 , G11C11/4094 , G11C11/4091 , G11C11/4074 , G11C11/4096 , G11C11/4099
Abstract: Memory devices are provided. A memory device includes a voltage generation circuit that includes an offset compensator configured to receive a reference voltage and an offset code and to link the offset code to the reference voltage. The voltage generation circuit includes a comparator configured to compare the reference voltage linked to the offset code with a bit line pre-charge voltage and to output driving control signals. The voltage generation circuit includes a driver configured to output the bit line pre-charge voltage at a target level of the reference voltage in response to the driving control signals. The voltage generation circuit includes a background calibration circuit configured to generate the offset code for performing control so that a target short current flows through an output node of the driver from which the bit line pre-charge voltage is output. Related methods of generating a bit line pre-charge voltage are also provided.
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3.
公开(公告)号:US20200082872A1
公开(公告)日:2020-03-12
申请号:US16517724
申请日:2019-07-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Young-hun Seo , Seung-hyun Cho , Chang-ho Shin , Yong-jae Lee
IPC: G11C11/4094 , G11C11/4091 , G11C11/4099 , G11C11/4096 , G11C11/4074
Abstract: Memory devices are provided. A memory device includes a voltage generation circuit that includes an offset compensator configured to receive a reference voltage and an offset code and to link the offset code to the reference voltage. The voltage generation circuit includes a comparator configured to compare the reference voltage linked to the offset code with a bit line pre-charge voltage and to output driving control signals. The voltage generation circuit includes a driver configured to output the bit line pre-charge voltage at a target level of the reference voltage in response to the driving control signals. The voltage generation circuit includes a background calibration circuit configured to generate the offset code for performing control so that a target short current flows through an output node of the driver from which the bit line pre-charge voltage is output. Related methods of generating a bit line pre-charge voltage are also provided.
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