公开(公告)号：US11600318B2

公开(公告)日：2023-03-07

申请号：US17497483

申请日：2021-10-08

申请人： Honeywell International Inc.

发明人： Keith Golke

IPC分类号： G11C11/4094 ,  G11C17/12 ,  G11C11/4074 ,  G11C11/4099

摘要： An apparatus for reading a bit of a memory array includes a bit cell column, voltage enhancement circuitry, and control circuitry. The voltage enhancement circuitry is configured to couple a bitline to a reference node. The control circuitry is configured to, in response to a read request for a bitcell element of a plurality of bitcell elements, couple a current source to the bitcell column such that a read current from the current source flows from the source line, through the bitcell column and the voltage enhancement circuitry, to the reference node and determine a state for the bitcell element based on a voltage between the source line and the reference node. The voltage enhancement circuitry is configured to generate, when the read current flows through the voltage enhancement circuitry, a voltage at the bitline that is greater than a voltage at the reference node.

公开(公告)号：US20230007890A1

公开(公告)日：2023-01-12

申请号：US17368705

申请日：2021-07-06

申请人： Macronix International Co., Ltd.

发明人： Teng-Hao YEH ,  Hang-Ting LUE ,  Cheng-Lin SUNG ,  Yung-Feng LIN

IPC分类号： G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/4074 ,  G11C16/10 ,  G11C16/28

摘要： A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

公开(公告)号：US11551744B2

公开(公告)日：2023-01-10

申请号：US17158767

申请日：2021-01-26

申请人： SK hynix Inc.

发明人： Chan Hui Jeong

IPC分类号： G11C11/4093 ,  G11C11/4099 ,  G11C5/06 ,  G11C11/4091 ,  G11C11/4094

摘要： A memory device according to the present technology includes a memory cell array configured to include planes having a plurality of memory cells, a page buffer connected to at least one memory cell among the memory cells through a bit line and configured to perform a sensing operation of reading data stored in the at least one memory cell connected to the bit line, a common reference voltage generator configured to generate a common reference voltage, a plurality of merged buffers configured to generate a reference signal using the common reference voltage, and control logic configured to control an operation of the common reference voltage generator and the merged buffers so that page buffer control signals generated based on the reference signal are supplied to the page buffer.

公开(公告)号：US11487655B2

公开(公告)日：2022-11-01

申请号：US17355192

申请日：2021-06-23

申请人： Silicon Motion, Inc.

发明人： Jian-Dong Du ,  Chia-Jung Hsiao ,  Tsung-Chieh Yang

IPC分类号： G06F12/02 ,  G11C11/4093 ,  G06F12/0882 ,  G11C11/4099 ,  G11C11/4074 ,  G06F13/16

摘要： The present invention provides a flash memory controller, wherein the flash memory controller is arranged to access a flash memory module, and the flash memory controller includes a ROM, a microprocessor and a timer. The ROM stores a program code, the microprocessor is configured to execute the program code to control the access of the flash memory module, and the timer is used to generate time information. In the operations of the flash memory controller, the microprocessor refers to the time information to perform dummy read operations upon at least a portion of the blocks, wherein the dummy read operations are not triggered by read commands from a host device.

公开(公告)号：US20220328090A1

公开(公告)日：2022-10-13

申请号：US17411699

申请日：2021-08-25

申请人： SK hynix Inc.

发明人： Chan Hui JEONG

IPC分类号： G11C11/4072 ,  G11C11/4074 ,  G11C11/4099 ,  G11C11/4076

摘要： An internal voltage generation circuit includes an enable control circuit configured to generate a final enable signal by limiting an activation time point of an enable signal to a point in time after a reset time, after the enable signal is inactivated. The internal voltage generation circuit also includes a start-up control circuit configured to perform a reset operation during the reset time and generate a start-up signal based on the final enable signal, a reference voltage generation circuit configured to generate a reference voltage based on the start-up signal, a current generation circuit configured to generate a reference current based on the reference voltage, and a voltage generation circuit configured to generate an internal voltage based on the reference current.

公开(公告)号：US11456026B2

公开(公告)日：2022-09-27

申请号：US17196969

申请日：2021-03-09

申请人： Winbond Electronics Corp.

发明人： Liang-Hsiang Chiu ,  Yu-Chieh Chen

IPC分类号： G11C11/4072 ,  G11C29/02 ,  G11C11/4074 ,  G11C11/4099 ,  G11C29/44 ,  G11C11/4076

摘要： A control device and a memory system are provided. The control device includes a first peripheral circuit group and a second peripheral circuit group. The first peripheral circuit group and a memory array are driven by a first voltage in a standby mode. The first peripheral circuit group provides a control command when recognizing that a command string is a deep power-down (DPD) execution command string. When receiving the control command, the second peripheral circuit group provides a DPD signal having a first logic value to stop providing the first voltage so that the memory system enters a DPD mode. In the DPD mode, when recognizing that the command string is a DPD exit command string, the second peripheral circuit group provides a DPD signal having a second logic value to provide the first voltage so that the memory system enters standby mode.

公开(公告)号：US20220208247A1

公开(公告)日：2022-06-30

申请号：US17445643

申请日：2021-08-23

申请人： Kioxia Corporation

发明人： Yuki INUZUKA

IPC分类号： G11C11/408 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/4074 ,  G11C5/06

摘要： A semiconductor memory device includes a first semiconductor pillar having i first memory cells on a first side and i second memory cells on a second side, a second semiconductor pillar having i third memory cells on a third side and i fourth memory cells on a fourth side, i first word lines (i is an integer of 4 or more) connected to the i first memory cells and the i third memory cells, i second word lines connected to the i second memory cells and the i fourth memory, and a driver. In writing data to the k-th (k is smaller than i and greater than 1) first memory cell, the driver supplies the k-th first word line with a first voltage larger than a reference voltage, and supplies the k-th second word line with a second voltage smaller than the reference voltage.

公开(公告)号：US11360848B2

公开(公告)日：2022-06-14

申请号：US16871329

申请日：2020-05-11

申请人： Micron Technology, inc.

发明人： Jongtae Kwak

IPC分类号： G06F11/00 ,  G06F11/10 ,  G11C11/22 ,  G11C11/406 ,  G11C29/52 ,  G11C11/4076 ,  G11C11/4099 ,  G11C7/10 ,  G11C29/04

摘要： Methods, systems, and devices for an error correcting code scrub scheme are described. A memory device may correct an error associated with a first data bit or a first parity bit of a plurality of data bits and a plurality of parity bits, respectively. The memory device may correct the error by reading each of the plurality of data bits and the plurality of parity bits from a memory array, and determining that an error associated with a single bit exists. The memory device may then correct the determined single-bit error, and may write the corrected bit directly back to the memory array.

公开(公告)号：US11289150B2

公开(公告)日：2022-03-29

申请号：US17196183

申请日：2021-03-09

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Youngmin Jo ,  Taehyo Kim ,  Daeseok Byeon ,  Seungwon Lee

IPC分类号： G11C11/40 ,  G11C11/4072 ,  G11C5/06 ,  G11C11/4093 ,  G11C11/4099

摘要： A memory system is provided. The memory system includes a memory device having a plurality of memory cells; and a memory controller configured to control the memory device to: store write data in first memory cells from among the plurality of memory cells, identify a current charge amount of a first cell string including at least one of the first memory cells and a current charge amount of a second cell string adjacent to the first cell string, and store dummy data in at least one memory cell connected to the first cell string or the second cell string based on the current charge amount of the first cell string and the current charge amount of the second cell string.

公开(公告)号：US11145358B2

公开(公告)日：2021-10-12

申请号：US16543315

申请日：2019-08-16

申请人： Micron Technology, Inc.

发明人： Scott J. Derner

IPC分类号： G11C7/12 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G11C7/06 ,  G11C8/08 ,  G11C11/4099 ,  G11C7/14

摘要： An apparatus includes a sense amplifier, a plurality of storage memory cells coupled to the sense amplifier via a first digit line, and a plurality of offset memory cells coupled to the sense amplifier via a second digit line. The plurality of storage memory cells and the plurality of offset memory cells can comprise an array of memory cells. Each of the storage memory cells and the offset memory cells can include a respective capacitor having a particular capacitance.