公开(公告)号：US20220399322A1

公开(公告)日：2022-12-15

申请号：US17734451

申请日：2022-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin KIM

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package is provided. The semiconductor package includes: a package substrate; a first semiconductor chip mounted on the package substrate; a second semiconductor chip mounted on the package substrate; an adhesive film provided on an upper surface the first semiconductor chip and an upper surface of the second semiconductor chip; and a third semiconductor chip attached to the first semiconductor chip, the second semiconductor chip by the adhesive film. The first and second semiconductor chips have different heights, and a thickness of the adhesive film at a portion thereof contacting the first semiconductor chip is different from a thickness of the adhesive film at a portion thereof contacting the second semiconductor chip.

公开(公告)号：US20230154855A1

公开(公告)日：2023-05-18

申请号：US17896797

申请日：2022-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin KIM

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L25/0657 ,  H01L23/5383 ,  H01L23/3128 ,  H01L23/5384 ,  H01L24/48 ,  H01L2225/06562 ,  H01L2224/48228 ,  H01L2224/48147

Abstract: A semiconductor package includes a package substrate including a substrate body having a lower surface and a upper surface, a lower wiring layer on the lower surface and including a land region, an upper wiring layer on the upper surface and electrically connected to the lower wiring layer, and a solder resist layer on the lower surface and including an opening exposing the land region. The semiconductor package further includes a semiconductor chip on the package substrate and having contact pads electrically connected to the upper wiring layer, and a mold part on the package substrate, wherein the package substrate further includes an open region defined by a portion of a bottom surface of the package substrate on which the solder resist layer is not present and that is adjacent to at least one edge of the package substrate on the bottom surface of the package substrate.

公开(公告)号：US20210407916A1

公开(公告)日：2021-12-30

申请号：US17176756

申请日：2021-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin KIM

IPC: H01L23/538 ,  H01L23/48 ,  H01L25/065

Abstract: A package substrate includes: a core insulation layer having first and second package regions and a boundary region between the first and second package regions; a first upper conductive pattern in the first package region; a second upper conductive pattern in the second package region; a first insulation pattern on the core insulation layer to partially expose the first and second upper conductive patterns, wherein the first insulation pattern includes a first trench at the boundary region, and first reinforcing portions in the first trench; a first lower conductive pattern in the first package region; a second lower conductive pattern in the second package region; and a second insulation pattern on the core insulation layer to partially expose the first and second lower conductive patterns, wherein the second insulation pattern includes a second trench at the boundary region, and second reinforcing portions in the second trench.

公开(公告)号：US20240274581A1

公开(公告)日：2024-08-15

申请号：US18437570

申请日：2024-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohoon KIM ,  Seungmin KIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L23/49822 ,  H01L2224/08235 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436 ,  H10B80/00

Abstract: A semiconductor package includes a package substrate, and a first semiconductor chip positioned on the package substrate. The first semiconductor chip includes a first inactive layer and a first active layer. The first inactive layer includes a high-density region, and the high-density region of the first inactive layer has a higher density than densities of other regions of the first inactive layer.

公开(公告)号：US20230121128A1

公开(公告)日：2023-04-20

申请号：US18081900

申请日：2022-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin KIM

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/48

Abstract: A package substrate includes: a core insulation layer having first and second package regions and a boundary region between the first and second package regions; a first upper conductive pattern in the first package region; a second upper conductive pattern in the second package region; a first insulation pattern on the core insulation layer to partially expose the first and second upper conductive patterns, wherein the first insulation pattern includes a first trench at the boundary region, and first reinforcing portions in the first trench; a first lower conductive pattern in the first package region; a second lower conductive pattern in the second package region; and a second insulation pattern on the core insulation layer to partially expose the first and second lower conductive patterns, wherein the second insulation pattern includes a second trench at the boundary region, and second reinforcing portions in the second trench.

公开(公告)号：US20230111555A1

公开(公告)日：2023-04-13

申请号：US17725729

申请日：2022-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin KIM

IPC: H01L25/16

Abstract: A semiconductor package includes a substrate having a passive element region, a peripheral region adjacent to the passive element region, and a remaining region, a first passive element on an upper surface of the passive element region, a first semiconductor chip on an upper surface of the remaining region, and a sealing portion covering the substrate, the first passive element, and the first semiconductor chip, wherein the peripheral region includes a first sub-region on a first side of the first passive element, a second sub-region on a second side opposite the first side, a third sub-region on a third side of the first passive element, and a fourth sub-region on a fourth side opposite the third side, and wherein a roughness of an upper surface of at least one of the first to fourth sub-regions is greater than a roughness of the upper surface of the remaining region.