公开(公告)号：US20250118600A1

公开(公告)日：2025-04-10

申请号：US18984957

申请日：2024-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Uihyoung Lee ,  Honyun Park ,  Jongseok Lee ,  Sewan Kim ,  Taesung Lee

IPC: H01L21/768 ,  C23C14/04

Abstract: A method of fabricating a semiconductor device includes forming a dielectric layer on a lower structure. The method includes forming an opening to penetrate through the dielectric layer. The method includes alternately repeating a first operation, in which a first sputtering deposition process is performed to form a first metal pattern in the opening, and a second operation, in which a second sputtering deposition process is performed to form a second metal pattern in the opening, two or more times to form a first metal layer. The method includes forming a second metal layer on the first metal layer in an electroplating manner, and planarizing the first and second metal layers. Moreover, first and second process times, during which the first sputtering deposition process and the second sputtering deposition process, respectively, are performed, are each about five seconds or less.

公开(公告)号：US12211745B2

公开(公告)日：2025-01-28

申请号：US17558699

申请日：2021-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Uihyoung Lee ,  Honyun Park ,  Jongseok Lee ,  Sewan Kim ,  Taesung Lee

IPC: H01L21/768 ,  H01L21/285

Abstract: A method of fabricating a semiconductor device includes forming a dielectric layer on a lower structure. The method includes forming an opening to penetrate through the dielectric layer. The method includes alternately repeating a first operation, in which a first sputtering deposition process is performed to form a first metal pattern in the opening, and a second operation, in which a second sputtering deposition process is performed to form a second metal pattern in the opening, two or more times to form a first metal layer. The method includes forming a second metal layer on the first metal layer in an electroplating manner, and planarizing the first and second metal layers. Moreover, first and second process times, during which the first sputtering deposition process and the second sputtering deposition process, respectively, are performed, are each about five seconds or less.

公开(公告)号：US20220359282A1

公开(公告)日：2022-11-10

申请号：US17558699

申请日：2021-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Uihyoung Lee ,  Honyun Park ,  Jongseok Lee ,  Sewan Kim ,  Taesung Lee

IPC: H01L21/768 ,  H01L21/285

Abstract: A method of fabricating a semiconductor device includes forming a dielectric layer on a lower structure. The method includes forming an opening to penetrate through the dielectric layer. The method includes alternately repeating a first operation, in which a first sputtering deposition process is performed to form a first metal pattern in the opening, and a second operation, in which a second sputtering deposition process is performed to form a second metal pattern in the opening, two or more times to form a first metal layer. The method includes forming a second metal layer on the first metal layer in an electroplating manner, and planarizing the first and second metal layers. Moreover, first and second process times, during which the first sputtering deposition process and the second sputtering deposition process, respectively, are performed, are each about five seconds or less.