公开(公告)号：US10379866B2

公开(公告)日：2019-08-13

申请号：US15654277

申请日：2017-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-hun Lee ,  Jae-un Park ,  Si-hoon Song ,  Myung-sun Kim

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/82 ,  G06F8/41

Abstract: An electronic apparatus generating compiled data used in a very long instruction word (VLIW) processor including a plurality of function units is provided. The electronic apparatus includes a storage and a processor configured to control the storage to store the compiled data in which a plurality of VLIW instructions are compiled, identify a VLIW instruction from the compiled data; and update, if a multi-cycle no operation (nop) instruction for the plurality of function units is identified within a cycle corresponding to a latency of the identified VLIW instruction and if an end cycle of another VLIW instruction is within the cycle corresponding to the latency of the identified VLIW instruction, the compiled data by including information on a cycle difference between an end cycle of the identified VLIW instruction and the end cycle of the another VLIW instruction in the multi-cycle nop instruction.

公开(公告)号：US10331455B2

公开(公告)日：2019-06-25

申请号：US15654277

申请日：2017-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-hun Lee ,  Jae-un Park ,  Si-hoon Song ,  Myung-sun Kim

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/82 ,  G06F8/41

Abstract: An electronic apparatus generating compiled data used in a very long instruction word (VLIW) processor including a plurality of function units is provided. The electronic apparatus includes a storage and a processor configured to control the storage to store the compiled data in which a plurality of VLIW instructions are compiled, identify a VLIW instruction from the compiled data; and update, if a multi-cycle no operation (nop) instruction for the plurality of function units is identified within a cycle corresponding to a latency of the identified VLIW instruction and if an end cycle of another VLIW instruction is within the cycle corresponding to the latency of the identified VLIW instruction, the compiled data by including information on a cycle difference between an end cycle of the identified VLIW instruction and the end cycle of the another VLIW instruction in the multi-cycle nop instruction.