公开(公告)号：US11263018B2

公开(公告)日：2022-03-01

申请号：US16462086

申请日：2017-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-seok Kwon ,  Jae-un Park ,  Dong-kwan Suh ,  Kang-jin Yoon

IPC: G06F9/38 ,  G06F9/30

Abstract: A vector processor is disclosed. The vector processor includes a plurality of register files provided to each of a plurality of single instruction multiple data (SIMD) lanes, storing each of a plurality of pieces of data, and respectively outputting input data to be used in a current cycle among the plurality of pieces of data, a shuffle unit for receiving a plurality of pieces of input data outputted from the plurality of register files, and performing shuffling such that the received plurality of pieces of input data respectively correspond to the plurality of SIMD lanes and outputting the same; and a command execution unit for performing a parallel operation by receiving input data outputted from the shuffle unit.

公开(公告)号：US10379866B2

公开(公告)日：2019-08-13

申请号：US15654277

申请日：2017-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-hun Lee ,  Jae-un Park ,  Si-hoon Song ,  Myung-sun Kim

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/82 ,  G06F8/41

Abstract: An electronic apparatus generating compiled data used in a very long instruction word (VLIW) processor including a plurality of function units is provided. The electronic apparatus includes a storage and a processor configured to control the storage to store the compiled data in which a plurality of VLIW instructions are compiled, identify a VLIW instruction from the compiled data; and update, if a multi-cycle no operation (nop) instruction for the plurality of function units is identified within a cycle corresponding to a latency of the identified VLIW instruction and if an end cycle of another VLIW instruction is within the cycle corresponding to the latency of the identified VLIW instruction, the compiled data by including information on a cycle difference between an end cycle of the identified VLIW instruction and the end cycle of the another VLIW instruction in the multi-cycle nop instruction.

公开(公告)号：US10331455B2

公开(公告)日：2019-06-25

申请号：US15654277

申请日：2017-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-hun Lee ,  Jae-un Park ,  Si-hoon Song ,  Myung-sun Kim

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/82 ,  G06F8/41

Abstract: An electronic apparatus generating compiled data used in a very long instruction word (VLIW) processor including a plurality of function units is provided. The electronic apparatus includes a storage and a processor configured to control the storage to store the compiled data in which a plurality of VLIW instructions are compiled, identify a VLIW instruction from the compiled data; and update, if a multi-cycle no operation (nop) instruction for the plurality of function units is identified within a cycle corresponding to a latency of the identified VLIW instruction and if an end cycle of another VLIW instruction is within the cycle corresponding to the latency of the identified VLIW instruction, the compiled data by including information on a cycle difference between an end cycle of the identified VLIW instruction and the end cycle of the another VLIW instruction in the multi-cycle nop instruction.

公开(公告)号：US10481867B2

公开(公告)日：2019-11-19

申请号：US15727093

申请日：2017-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-un Park ,  Jong-hun Lee ,  Ki-seok Kwon ,  Dong-kwan Suh ,  Kang-jin Yoon ,  Jung-uk Cho

IPC: G06F13/16 ,  G06F5/06 ,  G06F9/38 ,  G06F9/52

Abstract: A data input/output unit is provided. The data input/output unit which is connected to a processor, and receives and outputs data in sequence based on a first schedule includes a first input first output (FIFO) memory connected to an external unit and the processor; and a reordering buffer connected to one side of the FIFO memory, and store data outputted from, or inputted to, the FIFO memory in a plurality of buffer regions in sequence, and output data stored in one of the plurality of buffer regions based on a control signal provided from the processor.

公开(公告)号：US10185565B2

公开(公告)日：2019-01-22

申请号：US15100452

申请日：2014-11-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-un Park ,  Tai-song Jin ,  Do-hyung Kim ,  Suk-jin Kim

IPC: G06F9/30 ,  G06F15/78

Abstract: Provided are a method and an apparatus for controlling a register of a reconfigurable processor. The power of a register may be efficiently used by obtaining a command for each of a plurality of read ports of the register from a memory, obtaining activation information for each of the plurality of read ports from the obtained command, and determining an address value of each of the plurality of read ports on the basis of the obtained activation information.