公开(公告)号：US20240259176A1

公开(公告)日：2024-08-01

申请号：US18241565

申请日：2023-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungwook CHO ,  Subin YIM

IPC: H04L7/00

CPC classification number: H04L7/0025 ,  H04L7/0037 ,  H04L7/0087

Abstract: A receiving device includes a delay buffer configured to receive an analog signal and output a delayed analog signal, a phase interpolator configured to output a clock signal based on a phase compensation code signal and a reference clock signal, an analog-to-digital converter group configured to output a slope type determination signal indicating a slope of the analog signal based on the analog signal and the delayed analog signal, and a clock data restorer. The clock data restorer is configured to determine a curve type associated with a plurality of digital samples from the analog-to-digital converter group. The clock data restorer also evaluates a timing of the clock signal based on the curve type and the slope type determination signal, and outputs the phase compensation code signal to move the sample timing closer to an optimum timing.