公开(公告)号：US20240322807A1

公开(公告)日：2024-09-26

申请号：US18502502

申请日：2023-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mukul Agarwal ,  Subodh Prakash Taigor

IPC: H03K5/24 ,  H03K5/00

CPC classification number: H03K5/249 ,  H03K5/00006 ,  H03K19/20

Abstract: A method to control a clock speed of a dynamic comparator may include sensing, by a clock speed control circuit, an output of the dynamic comparator to determine at least one failure in the dynamic comparator. Thereafter, the method may include reducing, by the clock speed control circuit, a frequency of a clock signal used to control the clock speed of the dynamic comparator, based on the determined at least one failure in the dynamic comparator.

公开(公告)号：US12301109B2

公开(公告)日：2025-05-13

申请号：US18317458

申请日：2023-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ravindra Kumar Singh ,  Mihir Dhagat ,  Subodh Prakash Taigor

IPC: H02M3/07 ,  H02M1/38

Abstract: The present disclosure relates to a charge pump circuit with a six-phase clock. The charge pump circuit comprises a six-phase clock circuit and a gate boosting charge pump configured to receive a plurality of clock signals from the six-phase clock circuit. The six-phase clock circuit includes provides a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, and a sixth clock signal. The gate boosting charge pump is configured to enable a charge-sharing operation to share the stored amount of charges between a plurality of parasitic capacitors. The six-phase clock circuit is configured to provide a dead time between each of the first, second, third, fourth, fifth and sixth clock.

公开(公告)号：US20240322755A1

公开(公告)日：2024-09-26

申请号：US18410041

申请日：2024-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shubham Raj Singh ,  Ravindra Kumar Singh ,  Subodh Prakash Taigor

IPC: H03B5/04 ,  H03B5/24

CPC classification number: H03B5/04 ,  H03B5/24

Abstract: An oscillator includes first and second comparators, a first impedance network having a first trim element therein, and a second impedance network having a second trim element therein. The first impedance network is electrically connected to a first input terminal of the first comparator, and the second impedance network is electrically connected to a first input terminal of the second comparator. The first and second impedance networks are configured to cause an improvement in common mode variation within the first and second comparators, in response to trimming of at least one of the first and second trim elements.