公开(公告)号：US20250056792A1

公开(公告)日：2025-02-13

申请号：US18437865

申请日：2024-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Ho Lee ,  Yu Yeol Lee ,  Seung Hyun Kim ,  Seong Jae Byeon ,  Sung Duk Hong

IPC: H10B12/00

Abstract: A semiconductor memory device is provided that includes a bit line on a substrate, a protruded insulating pattern on the bit line, and in a channel trench, first and second channel patterns that extend along sidewalls of the channel trench, and spaced apart from the first channel pattern in the first direction, a channel interfacial layer that extends along the sidewalls of the channel trench, and is in contact with the first channel pattern and the second channel pattern, a first word line between the first channel pattern and the second channel pattern, a second word line between the first channel pattern and the second channel pattern, and is spaced apart from the first word line in the first direction and a first capacitor and a second capacitor, which are electrically connected to the first channel pattern and the second channel pattern.