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    Method of fabricating semiconductor light emitting device
    1.
    发明授权
    Method of fabricating semiconductor light emitting device 有权
    制造半导体发光器件的方法

    公开(公告)号：US09502605B2

    公开(公告)日：2016-11-22

    申请号：US14714223

    申请日：2015-05-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang Heon Han ,  Dong Yul Lee ,  Seung Hyun Kim ,  Jang Mi Kim ,  Suk Ho Yoon ,  Sang Jun Lee

    IPC: H01L33/00 ,  H01L33/06

    CPC classification number: H01L33/0075 ,  H01L33/0025 ,  H01L33/007 ,  H01L33/06 ,  H01L33/145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49107 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

    Abstract: A method of fabricating a semiconductor light emitting device includes forming a first conductivity type semiconductor layer, forming an active layer by alternately forming a plurality of quantum well layers and a plurality of quantum barrier layers on the first conductivity type semiconductor layer, and forming a second conductivity type semiconductor layer on the active layer. The plurality of quantum barrier layers include at least one first quantum barrier layer adjacent to the first conductivity type semiconductor layer and at least one second quantum barrier layer adjacent to the second conductivity type semiconductor layer. The forming of the active layer includes allowing the at least one first quantum barrier layer to be grown at a first temperature and allowing the at least one second quantum barrier layer to be grown at a second temperature lower than the first temperature.

    Abstract translation: 一种制造半导体发光器件的方法包括：形成第一导电型半导体层，通过在第一导电型半导体层上交替地形成多个量子阱层和多个量子势垒层来形成有源层，并形成第二导电型半导体层 导电型半导体层。 多个量子势垒层包括与第一导电类型半导体层相邻的至少一个第一量子势垒层和与第二导电类型半导体层相邻的至少一个第二量子势垒层。 活性层的形成包括允许至少一个第一量子势垒层在第一温度下生长并允许至少一个第二量子势垒层在低于第一温度的第二温度下生长。

    SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20250056792A1

    公开(公告)日：2025-02-13

    申请号：US18437865

    申请日：2024-02-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ju Ho Lee ,  Yu Yeol Lee ,  Seung Hyun Kim ,  Seong Jae Byeon ,  Sung Duk Hong

    IPC: H10B12/00

    Abstract: A semiconductor memory device is provided that includes a bit line on a substrate, a protruded insulating pattern on the bit line, and in a channel trench, first and second channel patterns that extend along sidewalls of the channel trench, and spaced apart from the first channel pattern in the first direction, a channel interfacial layer that extends along the sidewalls of the channel trench, and is in contact with the first channel pattern and the second channel pattern, a first word line between the first channel pattern and the second channel pattern, a second word line between the first channel pattern and the second channel pattern, and is spaced apart from the first word line in the first direction and a first capacitor and a second capacitor, which are electrically connected to the first channel pattern and the second channel pattern.

    Memory device with memory cell structure including ferroelectric data storage layer, and a first gate and a second gate
    3.
    发明授权
    Memory device with memory cell structure including ferroelectric data storage layer, and a first gate and a second gate 有权

    公开(公告)号：US10896711B2

    公开(公告)日：2021-01-19

    申请号：US16522121

    申请日：2019-07-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung Hwan Lee ,  Seung Hyun Kim ,  Yong Seok Kim ,  Jun Hee Lim ,  Kohji Kanamori

    IPC: G11C11/22 ,  H01L27/11585

    Abstract: A memory device includes memory cells, the memory cells each including a first gate, a second gate electrically isolated from the first gate, a first gate insulating layer including a data storage layer having a ferroelectric material and disposed between the first gate and a channel region, a second gate insulating layer disposed between the second gate and the channel region, a first switching cell connected between the memory cells and a source line, and a second switching cell connected between the memory cells and a bit line. The second switching cell includes a third gate, a fourth gate, a third gate insulating layer not including a data storage layer having the ferroelectric material and the third gate disposed between the third gate and the channel region, and a fourth gate insulating layer disposed between the fourth gate and the channel region.

    Method of fabricating semiconductor light emitting device
    5.
    发明授权
    Method of fabricating semiconductor light emitting device 有权

    公开(公告)号：US10304990B2

    公开(公告)日：2019-05-28

    申请号：US15341259

    申请日：2016-11-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang Heon Han ,  Dong Yul Lee ,  Seung Hyun Kim ,  Jang Mi Kim ,  Suk Ho Yoon ,  Sang Jun Lee

    IPC: H01L33/00 ,  H01L33/06 ,  H01L33/14

    Abstract: A method of fabricating a semiconductor light emitting device includes forming a first conductivity type semiconductor layer, forming an active layer by alternately forming a plurality of quantum well layers and a plurality of quantum barrier layers on the first conductivity type semiconductor layer, and forming a second conductivity type semiconductor layer on the active layer. The plurality of quantum barrier layers include at least one first quantum barrier layer adjacent to the first conductivity type semiconductor layer and at least one second quantum barrier layer adjacent to the second conductivity type semiconductor layer. The forming of the active layer includes allowing the at least one first quantum barrier layer to be grown at a first temperature and allowing the at least one second quantum barrier layer to be grown at a second temperature lower than the first temperature.

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