公开(公告)号：US20220075981A1

公开(公告)日：2022-03-10

申请号：US17464100

申请日：2021-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Bae PARK ,  Sung Han KIM ,  Sung Young YUN ,  Seon-Jeong LIM ,  Chul Joon HEO

IPC: G06K9/00 ,  G06F21/32 ,  G06F3/041

Abstract: An electronic device includes a display panel and a biometric sensor. The display panel includes a light emitter. The biometric sensor is stacked with the display panel and is configured to detect light emitted from the display panel and reflected by a recognition target that is external to the electronic device. The biometric sensor includes a silicon substrate and a photoelectric conversion element on the silicon substrate. The photoelectric conversion element includes a photoelectric conversion layer having wavelength selectivity.

公开(公告)号：US20240014119A1

公开(公告)日：2024-01-11

申请号：US18370914

申请日：2023-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Han KIM ,  Masazumi Amagai ,  Ju Ho Kim ,  Tae Sung Jeong

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/49838 ,  H01L24/06 ,  H01L24/14 ,  H01L23/5389 ,  H01L23/49816 ,  H01L2224/0401 ,  H01L2924/1431 ,  H01L2924/3511 ,  H01L2224/18 ,  H01L2924/1433 ,  H01L23/3128

Abstract: A fan-out semiconductor package includes connection pads of a semiconductor chip that are redistributed and electrically connected to connection terminals by an interconnection member. In the fan-out semiconductor package, disposition forms of vias and pads in the interconnection member are designed so that stress may be reduced, such that reliability is improved.

公开(公告)号：US20210375739A1

公开(公告)日：2021-12-02

申请号：US17401376

申请日：2021-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Han KIM ,  Masazumi AMAGAI ,  Ju Ho KIM ,  Tae Sung JEONG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538

Abstract: A fan-out semiconductor package includes connection pads of a semiconductor chip that are redistributed and electrically connected to connection terminals by an interconnection member. In the fan-out semiconductor package, disposition forms of vias and pads in the interconnection member are designed so that stress may be reduced, such that reliability is improved.