公开(公告)号：US20160371092A1

公开(公告)日：2016-12-22

申请号：US15257063

申请日：2016-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Boem PARK ,  Jin-Sung PARK ,  Ara CHO

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3865 ,  G06F9/30145 ,  G06F11/3688

Abstract: A verification method of a system on chip includes receiving a test generator and an exception handler; generating, by the test generator, a test program including an exception-causing instruction based on a test template; executing a first instruction at a first operating state as the test program is executed; stopping the execution of the test program and performing a fixed instruction sequence included in the exception handler when the exception-causing instruction is executed during the execution of the test program; and resuming the test program from a second instruction at a second operating state set after the fixed instruction sequence is performed, the second instruction corresponding to an address adjacent to an address of the exception-causing instruction.