公开(公告)号：US20240349487A1

公开(公告)日：2024-10-17

申请号：US18432408

申请日：2024-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungnam Lyu ,  Hyojung Noh ,  Minwoo Yang ,  Byounghoon Lee ,  Eulji Jeong

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315 ,  H10B12/482

Abstract: A gate structure may include a first conductive pattern, a second conductive pattern on the first conductive pattern and including polysilicon doped with impurities, and a gate insulation pattern on sidewalls of the first and second conductive patterns. A capping layer including a semiconductor material or an insulating material may be disposed under the first conductive pattern. The first conductive pattern may include metal grains. At least one of the metal grains may extend from an upper surface of the capping layer to a lower surface of the second conductive pattern, and may contact the upper surface of the capping layer and the lower surface of the second conductive pattern.