INTEGRATED CIRCUIT INCLUDING PHASE LOCKED LOOP CIRCUIT

    公开(公告)号:US20200021298A1

    公开(公告)日:2020-01-16

    申请号:US16216226

    申请日:2018-12-11

    Abstract: A phase locked loop circuit includes a voltage controlled oscillator configured to output a clock signal having a predetermined frequency based in a control voltage, a phase frequency detector configured to compare the clock signal with a reference signal to output a first control signal and a second control signal, a charge pump configured to output the control voltage based on the first control signal and the second control signal, a voltage supply including an output terminal connected to an output terminal of the charge pump by a transmission switch, and a leakage remover circuit connected to the transmission switch and configured to remove a leakage current flowing through the transmission switch while the transmission switch is turned-off.

    PIXEL CLOCK GENERATOR, METHOD OF OPERATING THE SAME, AND APPARATUSES INCLUDING THE PIXEL CLOCK GENERATOR
    3.
    发明申请
    PIXEL CLOCK GENERATOR, METHOD OF OPERATING THE SAME, AND APPARATUSES INCLUDING THE PIXEL CLOCK GENERATOR 有权
    像素时钟发生器,其操作方法以及包括像素时钟发生器的装置

    公开(公告)号:US20140036150A1

    公开(公告)日:2014-02-06

    申请号:US13959067

    申请日:2013-08-05

    CPC classification number: H03B21/025 H04N5/04 H04N5/123

    Abstract: A method of operating a pixel clock generator (PCG), the method including generating N clock signals according to a control voltage signal, the N clock signals having different phases and N being a natural number; generating M frequency-divided clock signals based on the N clock signals, the M frequency-divided clock signals having different phases and M being a natural number greater than N; and generating a pixel clock signal based on at least two selected ones of the M frequency-divided clock signals.

    Abstract translation: 一种操作像素时钟发生器(PCG)的方法,该方法包括根据控制电压信号产生N个时钟信号,N个时钟信号具有不同的相位,N是自然数; 基于N个时钟信号产生M个分频时钟信号,具有不同相位的M个分频时钟信号,M是大于N的自然数; 以及基于所述M个分频时钟信号中的至少两个所选择的时钟信号产生像素时钟信号。

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