公开(公告)号：US20170048057A1

公开(公告)日：2017-02-16

申请号：US15197746

申请日：2016-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do-Hyung KIM ,  Tae-Ik KIM

IPC: H04L7/033 ,  H04L27/20 ,  H04W4/00 ,  H03L7/18

CPC classification number: H04L7/0331 ,  H03L7/18 ,  H04L27/20 ,  H04W4/80

Abstract: Provided are a semiconductor device including a modulator for PSK communication and a semiconductor device including a demodulator for PSK communication, and a PSK communication system. The semiconductor device includes a reference clock generator to generate a reference clock signal, a phase locked loop (PLL) to receive the reference clock signal and generate a first clock signal, an integer divider circuit to generate a second clock signal by delaying a rising edge of the reference clock signal by a product of a predetermined integer value included in transmission data and a phase interval, and a processing unit to generate a first transmission signal. The first transmission signal is phase-shifted from a first rising edge of the second clock signal. The phase interval is dependent on a ratio of the frequency of the first clock signal to the frequency of the reference clock signal.

Abstract translation: 提供一种包括用于PSK通信的调制器和包括用于PSK通信的解调器的半导体器件和PSK通信系统的半导体器件。 半导体器件包括用于产生参考时钟信号的参考时钟发生器，接收参考时钟信号并产生第一时钟信号的锁相环（PLL），整数分频器电路，通过延迟上升沿产生第二时钟信号 以及包括在发送数据中的预定整数值与相位间隔的乘积的参考时钟信号，以及产生第一发送信号的处理单元。 第一发送信号从第二时钟信号的第一上升沿相移。 相位间隔取决于第一时钟信号的频率与参考时钟信号的频率之比。

公开(公告)号：US20160056826A1

公开(公告)日：2016-02-25

申请号：US14632468

申请日：2015-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-Seok KIM ,  Tae-Ik KIM ,  Ji-Hyun KIM

IPC: H03L7/089 ,  H02M3/04

CPC classification number: H03L7/0891 ,  H02M3/04

Abstract: Provided are a semiconductor device and a phase-locked loop (PLL) including the same. The semiconductor device including an output node from which an output signal is output, a first transistor which has a drain connected to the output node and is gated by a first signal to increase a voltage level of the output node, a second transistor which has a drain connected to the output node, is gated by a second signal which is a complementary signal of the first signal, and reduces the voltage level of the output node, a pull-up circuit which provides a first compensation current varying according to the voltage level of the output node to a source of the first transistor, and a pull-down circuit which provides a second compensation current varying according to the voltage level of the output node to a source of the second transistor.

Abstract translation: 提供了包括其的半导体器件和锁相​​环（PLL）。 所述半导体器件包括输出信号被输出的输出节点，具有连接到所述输出节点的漏极并由第一信号选通以增加所述输出节点的电压电平的第一晶体管，具有 连接到输出节点的漏极由作为第一信号的互补信号的第二信号选通，并且降低输出节点的电压电平，提供根据电压电平变化的第一补偿电流的上拉电路 的输出节点连接到第一晶体管的源极;以及下拉电路，其提供根据输出节点的电压电平而变化到第二晶体管的源极的第二补偿电流。