公开(公告)号：US10734493B2

公开(公告)日：2020-08-04

申请号：US16029993

申请日：2018-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hauk Han ,  Je-hyeon Park ,  Do-hyung Kim ,  Tae-yong Kim ,  Keun Lee ,  Jeong-gil Lee ,  Hyun-seok Lim

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/786

Abstract: A semiconductor memory device may include a substrate, gate electrode structures stacked on the substrate, insulation patterns between the gate electrode structures, vertical channels penetrating through the gate electrode structures and the insulation patterns, and a data storage pattern. The vertical channels may be electrically connected to the substrate. The data storage pattern may be arranged between the gate electrode structures and the vertical channels. Each of the gate electrode structures may include a barrier film, a metal gate, and a crystal grain boundary plugging layer. The crystal grain boundary plugging layer may be between the barrier film and the metal gate.

公开(公告)号：US20190013388A1

公开(公告)日：2019-01-10

申请号：US16029993

申请日：2018-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hauk Han ,  Je-Hyeon Park ,  Do-hyung Kim ,  Tae-yong Kim ,  Keun Lee ,  Jeong-gil Lee ,  Hyun-seok Lim

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor memory device may include a substrate, gate electrode structures stacked on the substrate, insulation patterns between the gate electrode structures, vertical channels penetrating through the gate electrode structures and the insulation patterns, and a data storage pattern. The vertical channels may be electrically connected to the substrate. The data storage pattern may be arranged between the gate electrode structures and the vertical channels. Each of the gate electrode structures may include a barrier film, a metal gate, and a crystal grain boundary plugging layer. The crystal grain boundary plugging layer may be between the barrier film and the metal gate.